Modulation of the workfunction of Ni fully silicided gates by doping: Dielectric and silicide phase effects

IEEE Electron Device Letters

Volumn 27, Issue 2, 2006, Pages 99-101

  Pawlak, M A ^a,b   Lauwers, A ^b   Janssens, T ^b   Anil, K G ^b   Opsomer, K ^b,c   Maex, K ^b,c   Vantomme, A ^a   Kittl, J A ^b,d  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

^c Katholieke Universiteit Leuven   (Belgium)

^d TEXAS INSTRUMENTS   (United States)

Author keywords

Dopants; Full silicidation; High ; Metal gate; Ni2Si; Ni31Si12; NiSi; SiO2; Workfunction (WF)

Indexed keywords

DIELECTRIC MATERIALS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; MODULATION; NICKEL; PHASE INTERFACES; SEMICONDUCTING SILICON COMPOUNDS;

DOPANTS; FULL SILICIDATION; METAL GATE; NICKEL FULLY SILICIDED GATES;

SEMICONDUCTOR DOPING;

EID: 31544447747     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.862677     Document Type: Article

References (13)

1. A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G. Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, and K. Okumura, "High performance metal gate MOSFETs fabricated by CMP for 0.1 μm regime," in IEDM Tech. Dig., 1998, pp. 785-788.
2. W. P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, and M.-R. Lin, "Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates," in IEDM Tech. Dig., 2002, pp. 367-370.
3. J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, J. Ott, C. Cabral, M. Ieong, Jr., and W. Haensch, "Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SUS)," in IEDM Tech. Dig., 2003, pp. 315-318.
4. K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, "Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45 nm-node LSTP and LOP devices," in IEDM Tech. Dig., 2004, pp. 91-94.
5. J. A. Kittl, A. Veloso, A. Lauwers, K. G. Anil, C. Demeurisse, S. Kubicek, M. Niwa, A J. H. van Dal, O. Richard, M. A. Pawlak, A Jurczak, C. Vrancken, T. Chiarella, S. Brus, K. Maex, and S. Biesemans, "Scalability of Ni FUSI gate processes: Phase and Vt control to 30 mn gate lengths," in Symp. VLSI Tech. Dig., 2005, pp. 72-73.
6. J. H. Sim, H. C. Wen, J. P. Lu, and D.-L. Kwong, "Dual work function metal gates using full nickel silicidation of doped poly-Si," IEEE Electron Device Lett., vol. 24, no. 10, pp. 631-633, Oct. 2003.
7. C. Cabral, J. Kedzierski, Jr., B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carruthers, and R. Jammy, "Dual work-function fully silicided metal gate," in VLSI Tech. Dig., 2004, p. 184.
8. R. Jha, J. Gurganos, Y. H. Kim, R. Choi, and J. Lee, "A capacitance-based methodology for work function extraction of metals on high-κ," IEEE Electron Device Lett., vol. 25, no. 6, pp. 420-422, Jun. 2004.
9. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, "Fermi level pinning at the PolySi/metal oxide interface," in VLSI Symp. Tech. Dig., 2003, p. 9.
10. 2 related high-κ dielectrics interfaces," in VLSI Symp. Tech. Dig., 2004, p. 108.
11. 2Si formation," Appl. Phys. Lett., vol. 87, p. 181 910, 2005.
12. G. Pourtois, A. Lauwers, J. A. Kittl, L. Pantisano, B. Soree, S. De Gendt, W. Magnus, M. Heyens, and K. Maex, "First-principle calculations on gate dielectric interfaces: On the origin of work function shifts," Microelectron. Eng., vol. 80, pp. 272-279, 2005.
13. M. Copel, R. P. Pezzi, and C. Cabral, Jr., "Interfacial segregation of dopants in fully siticided metal-oxide-semiconductor gates," Appl. Phys. Lett., vol. 86, p. 251 904, 2005.