Scalability of Ni FUSI gate processes: Phase and Vt control to 30 nm gate lengths

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 72-73

  Kittl, J A ^b   Veloso, A ^a   Lauwers, A ^a   Anil, K G ^a   Demeurisse, C ^a   Kubicek, S ^a   Niwa, M ^c   Van Dal, M J H ^d   Richard, O ^a   Pawlak, M A ^a   Jurczak, M ^a   Vrancken, C ^a   Chiarella, T ^a   Brus, S ^a   Maex, K ^a   Biesemans, S ^a  

^a IMEC   (Belgium)

^b TEXAS INSTRUMENTS   (Belgium)

^c Matsushita   (Belgium)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

FERMI LEVEL; MOS DEVICES; THERMAL EFFECTS;

FERMI LEVEL UNPINNING; PHASE CONTROL ISSUES; SILICIDATION; THERMAL BUDGETS;

PHASE CONTROL;

EID: 31544465605     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469217     Document Type: Conference Paper

References (5)

1. B. Tavel et al., IEDM Tech. Dig., 825 (2001);
2. J. Kedzierski et al.,IEDM Tech. Dig., 247 (2002), 441 (2003);
3. K. G. Anil et al., Symp. VLSI Tech., 190 (2004);
4. A. Veloso et al., IEDM Tech. Dig., 855 (2004);
5. K. Takahashi et al., IEDM Tech. Dig., 91 (2004)