Dynamic and transparent binary translation

Computer

Volumn 33, Issue 3, 2000, Pages 54-59

  Gschwind, Michael ^a   Altman, Erik R ^b   Sathaye, Sumedh ^c   Ledak, Paul ^d   Appenzeller, David ^e  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^b MCGILL UNIVERSITY   (Canada)

^c NORTH CAROLINA STATE UNIVERSITY   (United States)

^d IBM Server Architecture Development   (United States)

^e DREXEL UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; OPTIMIZATION; PROGRAM COMPILERS; PROGRAM INTERPRETERS; PROGRAM TRANSLATORS; REDUCED INSTRUCTION SET COMPUTING; ROM; SCHEDULING;

BINARY TRANSLATION OPTIMIZED ARCHITECTURE; CYCLE PER INSTRUCTION; DYNAMIC TRANSLATION; INDEPENDENT SOFTWARE VENDOR; INSTRUCTION LEVEL PARALLELISM; TRANSPARENT BINARY TRANSLATION;

SOFTWARE ENGINEERING;

EID: 0033889996     PISSN: 00189162     EISSN: None     Source Type: Journal    
DOI: 10.1109/2.825696     Document Type: Article

References (6)

1. R. Sites et al., "Binary Translation," Digital Technical J., Dec. 1992, pp. 137-152.
2. K. Ebcioǧlu and E. Altman, "DAISY: Dynamic Compilation for 100 Percent Architectural Compatibility," Proc. ISCA24, ACM Press, New York, 1997, pp. 26-37.
3. K. Ebcioǧlu et al., "Execution-Based Scheduling for VLIW Architectures," Proc. Europar99, Lecture Notes in Computer Science 1685, Springer Verlag, Berlin, 1999, pp. 1269-1280.
4. K. Pettis and R.C. Hanson, "Profile Guided Code Positioning," Proc. 1990 SIGPLAN PLDI, ACM Press, New York, 1990, pp. 16-27.
5. S. Sathaye et al., "BOA: Targeting MultiGigahertz with Binary Translation," IEEE TCCA Newsletter, Fall 1999, pp. 2-11.
6. E. Altman et al., BOA: The Architecture of a Binary Translation Processor, IBM Research Report RC21665, IBM, Yorktown Heights, N.Y., 2000.