Formal verification of an Intel XScale processor model with scoreboarding, specialized execution pipelines, and impress data-memory exceptions

Proceedings - 1st ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE 2003

Volumn , Issue , 2003, Pages 65-74

  Srinivasan, S K ^a   Velev, M N ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Formal verification; Pipelines

Indexed keywords

FORMAL METHODS; PIPELINE PROCESSING SYSTEMS; PIPELINES; REDUCED INSTRUCTION SET COMPUTING;

AUTOMATIC TOOL FLOW; DATA MEMORY; DECISION PROCEDURE; MULTIPLY-AND-ACCUMULATE; PROCESSOR MODELING; RISC PROCESSORS; SCOREBOARDING; VARIABLE LATENCIES;

FORMAL VERIFICATION;

EID: 3042639039     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2003.1210090     Document Type: Conference Paper

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