Scaling properties of the tunneling field effect transistor (TFET): Device and circuit

Solid-State Electronics

Volumn 50, Issue 1, 2006, Pages 44-51

  Nirschl, Th ^a,b   Henzler, St ^a   Fischer, J ^a   Fulde, M ^a   Bargagli Stoffi, A ^a   Sterkel, M ^a   Sedlmeir, J ^b   Weber, C ^b   Heinrich, R ^b   Schaper, U ^b   Einfeld, J ^b   Neubert, R ^b   Feldmann, U ^b   Stahrenberg, K ^b   Ruderer, E ^b   Georgakos, G ^b   Huber, A ^b   Kakoschke, R ^b   Hansch, W ^a   Schmitt Landsiedel, D ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Scaling; TCMOS; Temperature dependence; TFET

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DEGRADATION; ELECTRIC POWER UTILIZATION; ELECTRON TUNNELING; MOSFET DEVICES;

SCALING; TCMOS; TEMPERATURE DEPENDENCE; TFET;

FIELD EFFECT TRANSISTORS;

EID: 30344477991     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2005.10.045     Document Type: Conference Paper

References (23)

1. Nirschl Th, Wang P-F, Webe C, Sedlmeir J, Heinrich R, Kakoschke R, et al. The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes. In: Electron devices meeting, 2004. IEDM technical digest IEEE international. 2004. p. 195-8.
2. Shockley W, Hopper WW. The surface controlled avalanche transistor. In: WESCON, proceedings of 1964. p. 12.1.
3. Fischer W. Field induced tunnel diode. 1973.
4. S. Banerjee, W. Richardson, J. Coleman, and A. Chatterejee A new three-terminal tunnel device IEEE Electron Dev Lett 8 8 1987 347 348
5. J. Koga, and A. Toriumi Three-terminal silicon surface junction tunneling device for room temperature operation IEEE Electron Dev Lett 20 10 1999 529 531
6. T. Baba Proposal for surface tunnel transistor Jpn J Appl Phys 31 4B 1992 L455 L457
7. W.M. Reddick, and G.A.J. Amaratunga Silicon surface tunnel transistor Appl Phys Lett 67 4 1995 494 496
8. W. Hansch, C. Fink, J. Schulze, and I. Eisele A vertical MOS-gated Esaki tunneling transistor in silicon Thin Solid Films 369 2000 387 389
9. Girish NV, Jhaveri R, Woo JCS. Tunnel source MOSFET: a novel high performance transistor. In: Silicon nanotechnology workshop (SNW), Proc of 2004.
10. C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, and D. Fraboulet Lateral interband tunneling transistor in silicon-on-insulator Appl Phys Lett 84 10 2004 1780 1782
11. H. Kawaura, T. Sakamoto, and T. Baba Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal oxide semiconductor field effect transistors Appl Phys Lett 76 25 2000 3810 3812
12. P.-F. Wang, Th. Nirschl, D. Schmitt-Landsiedel, and W. Hansch Simulation of the Esaki-tunneling FET Solid-State Electron 47 7 2003 1131 1248
13. ITRS Road-Map, International technology road-map for semiconductor, Available from: http://public.itrs.net/, 2003.
14. 2 6t memory cell and multi-Vth device. In: accepted at ESSDERC. 2005.
15. Schiml T, Biesemans S, Brase G, Burrell L, Cowley A, Chen KC, et al. A 0.13 m CMOS platform with Cu/low-k interconnects for system on chip applications. In: Symposium on VLSI technology, Proceedings of 2001.
16. Huang S-F, Lin C-Y, Huang Y-S, Schafbauer T, Eller M, Cheng Y-C, et al. High performance 50 nm CMOS devices for microprocessor and embedded processor core applications. In: International electron devices meeting (IEDM), Technical digest of 2001.
17. Luo Z, Steegenand A, Eller M, Mann R, Baiocco C, Nguyen P, et al. High performance and low-power transistors integrated in 65 nm bulk CMOS technology. In: International electron device meeting (IEDM), Digest of Technical Papers, 2004.
18. Nirschl Th, Schaper U, Einfeld J, Henzler St, Sterkel M, Singer J, et al. Impact of mask alignment on the tunneling field effect transistor (TFET). In: International conference on microelectronic test-structures (ICMTS), Proceedings of 2005.
19. Nirschl T, Wang P-F, Hansch W, Schmitt-Landsiedel D. The tunnelling field effect transistors (TFET): the temperature dependence, the simulation model, and its application. In: Circuits and systems, 2004. ISCAS '04. Proceedings of the 2004 international symposium. 2004, vol. 3. p. III-713-16.
20. Nirschl Th, Henzler St, Fischer J, Fulde B, Bargagli-Stoffi A, Sterkel M, et al. Scaling down the tunneling field effect transistor (TFET) from the 130 nm to the 65 nm CMOS process flow. In: Workshop on ultimate integration of silicon (ULIS), Proceedings of 2005.
21. E. Seevinck, F.J. List, and J. Lohstroh Static-noise margin analysis of MOS SRAM cells IEEE J Solid-State Circ (JSSC) 22 5 1987 748 754
22. Nirschl Th, Ostermayr M, Olbrich A, Vietzke D, Omer M, Linnenbank C, et al. MALTY-A memory test structure for analysis in the early phase of the technology development, In: European symposium on reliability of electron devices, failure physics and analysis (ESREF). 2003. p. A2, Microelectronics Reliability.
23. Medici User Guide Version V-2003.12, Synopsys, 2003.