Impact of mask alignment on the Tunneling Field Effect Transistor (TFET)

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2005, Pages 43-46

  Nirschl, Th ^a,b   Schaper, U ^b   Einfeld, J ^b   Henzler, St ^a,b   Sterkel, M ^a   Singer, J ^b   Fulde, M ^a   Hansch, W ^a   Georgakos, G ^b   Schmitt Landsiedel, D ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; MICROELECTRONICS;

LAYER OVERLAPPING; SOURCE EXTENSION; TEST-STRUCTURES;

MASKS;

EID: 27644461248     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Th. Nirschl et al., "Complementary Tunneling Field Effect Transistors (TFETs) fabricated in 130nm and 90nm Industrial CMOS Processes", IEDM 2004.
2. S. M. Sze, "Physiscs of Semiconductor Devices", ISBN 0-471-05661-8, 1981.
3. Medici User Guide, Version V-2003.12, Dec. 2003, Synopsys.