Practical slicing and non-slicing block-packing without simulated annealing

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 282-287

  Chan, Hayward H ^a   Markov, Igor L ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Block packing; Branch and bound; Evaluation; Floorplanning; Hierarchical; Large scale; Optimal; Slicing; Soft blocks

Indexed keywords

ALGORITHMS; BENCHMARKING; OPTIMIZATION; PROBLEM SOLVING; SIMULATED ANNEALING; TREES (MATHEMATICS); VECTORS;

BRANCH-AND-BOUND; FLOORPLANNING; HIERARCHICAL; LARGE SCALE; OPTIMAL; SLICING; SOFT BLOCKS;

VLSI CIRCUITS;

EID: 2942692522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/988952.989020     Document Type: Conference Paper

References (20)

1. S.N. Adya, I.L. Markov, "Fixed-outline Floorplanning: Enabling Hierarchical Design," IEEE Trans. on VLSI 11(6), pp. 1120-1135, 2003. http://vlsicad.eecs.umich.edu/BK/parquet/
2. A.E. Caldwell, A.B. Kahng, and I.L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout," IEEE Trans. on CAD, 19(11), pp. 1304-1314, 2000.
3. H.H. Chan and I.L. Markov, "Practical Slicing and Non-slicing Block-Packing without Simulated Annealing," CSE-TR-487-04, The University of Michigan, 2004.
4. Y.-C. Chang et al., "B*-trees: A New Representation for Non-Slicing Floorplans," DAC2000, pp. 458-463.
5. J. Cong, G. Nataneli, M. Romesis, J. Shinnerl, "An Area-Optimality Study of Floorplanning," to appear in ISPD 2004.
6. P.-N. Quo, C.-K. Cheng, T. Yoshimura, "An O-tree Representation of Non-Slicing Floorplan and Its Applications," DAC1999, pp. 268-273.
7. X. Hong et al., "Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan," ICCAD 2000, pp. 8-12.
8. M. Lai and D. Wong, "Slicing Tree Is a Complete Floorplan Representation," DATE 2001, pp. 228-232.
9. H.-C Lee, Y.-W Chang, J.-M Hsu, and H.H. Yang, "Multilevel Floorplanning/Placement for Large-Scale Modules Using B*-Trees," DAC 2003, pp. 812-817.
10. J.-M. Lin and Y.-W. Chang, "TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans," DAC 2002, pp. 842-847.
11. I. Mandoiu, "Multi-Project Reticle Floorplanning and Wafer Dicing," to appear in ISPD 2004.
12. H. Murata et al., "VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair," IEEE Trans on CAD 15(12), pp. 1518-1524, 1996.
13. S. Nakatake et al., "Module Placement on BSG-structure and IC Layout Applications," ICCAD 1996, pp. 484-491.
14. H. Onodera, Y. Taniguchi, and K. Tamaru, "Branch-and-Bound Placement for Building Block Layout," DAC 1991, pp. 433-439.
15. D. F. Wong and C. L. Liu, "A New Algorithm for Floorplan Design," DAC 1986, pp. 101-107.
16. J. Xu, P.-N. Guo, and C.-K. Cheng, "Cluster Refinement for Block Placement," DAC 1997, pp. 762-765.
17. B. Yao et al., "Floorplan Representations: Complexity and Connections," ACM Trans. on Design Autom. of Electronic Systems 8(1), pp. 55-80, 2003.
18. http://cc.ee.ncu.edu.tw/~ywchang/research.html
19. http://vlsicad.eecs.umich.edu/BK/BloBB/
20. http://vlsicad.eecs.umich.edu/BK/CornpaSS/