Multi-project reticle floorplanning and wafer dicing

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2004, Pages 70-77

  Kahng, Andrew B ^a   Mǎndou, Ion ^b   Wang, Qinke ^a   Xu, Xu ^a   Zelikovsky, Alex Z ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CONNECTICUT   (United States)

^c GEORGIA STATE UNIVERSITY   (United States)

Author keywords

Multi Project Wafers; Reticle Design; Wafer Dicing

Indexed keywords

ALGORITHMS; ANNEALING; COMPUTER SIMULATION; MATHEMATICAL PROGRAMMING; VLSI CIRCUITS; WORLD WIDE WEB;

CONFLICT GRAPHS; RETICLE DESIGN; WAFER DICING;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 2942682814     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/981066.981082     Document Type: Conference Paper

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