A fast algorithm for identifying good buffer insertion candidate locations

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2004, Pages 47-52

  Alpert, Charles J ^a   Hrkic, Milos ^a   Quay, Stephen T ^a  

^a NONE

Author keywords

Buffer insertion; Global routing; Physical synthesis; Planning

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; OPTICAL INTERCONNECTS; ROUTERS; TOPOLOGY;

BUFFER INSERTION; GLOBAL ROUTING; PHYSICAL SYNTHESIS;

VLSI CIRCUITS;

EID: 2942678874     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/981066.981076     Document Type: Conference Paper

References (18)

1. C. J. Alpert and A. Devgan, "Wire Segmenting for Improved Buffer Insertion", IEEE/ACM Design Automation Conf., 1997, pp. 588-593.
2. C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer Insertion for Noise and Delay Optimization", IEEE/ACM Design Automaton Conf., 1998, pp. 362-367.
3. C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer Insertion with Accurate Gate and Interconnect Delay Computation", IEEE/ACM Design Automation Conf., 1999, pp. 479-484.
4. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, and A. J. Sullivan, "Buffered Steiner Trees for Difficult Instances", IEEE Trans. on Computer-Aided Design, 21 (1), 2002, pp. 3-14.
5. C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. G. Villarrubia, "A Practical Methodology for Early Buffer and Wire Resource Allocation", IEEE/ACM Design Automation Conference, 2001, pp. 189-195.
6. T. H. Cormen, C. E. Liserson, R. L. Riyest, and C. Stein. Introduction to Algorithms, Second Edition. MIT Press, 2001.
7. J. Cong, "Challenges and Opportunities for Design Innovations in Nanometer Technologies", in SRC Working Papers, Dec. 1997.
8. J. Cong, T. Kong and D.Z. Pan, "Buffer Block Planning for Interconnect-Driven Floorplanning", IEEE/ACM Intl. Conf. on Computer-Aided Design, 1999, pp. 358-363.
9. S. Dhar and M. A. Franklin, "Optimum Buffer Circuits for Driving Long Uniform Lines", IEEE Journal of Solid-State Circuits, 26(1), 1991, pp. 32-40.
10. Y. Gao and D. F. Wong, "A Graph Based Algorithm for Optimal Buffer Insertion Under Accurate Delay Models", Design Automation and Test in Europe, 2001, pp. 535-539.
11. M. Lai and D. F. Wong, "Maze Routing with Buffer Insertion and Wiresizing", IEEE/ACM Design Automation Conf., 2000, pp. 374-378.
12. J. Lillis, C.-K. Cheng, T.-T. Y. Lin, and C.-Y. Ho, "New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing", 33th IEEE/ACM Design Automation Conference, 1996, pp. 395-400.
13. J. Lillis, C.-K. Cheng and T.-T. Y. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model", IEEE Journal of. Solid-State Circuits, 31(3), 1996, 437-447.
14. J. Lillis, C.-K. Cheng and T.-T. Y. Lin, "Simultaneous Routing and Buffer Insertion for High Performance Interconnect", Sixth Great Lakes Symposium on VLSI, 1996, pp. 148-153.
15. T. Okamoto and J. Cong, "Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization", IEEE/ACM International Conference on Computer-Aided Design, 1996, pp. 44-49.
16. P. Saxena, N. Menezes, P. Cocchini, and D. A. Kirkpatrick, "The Scaling Challenge: Can Correct-by-Construction Design Help?", Proc. Intl. Symposium on Physical Design, 2003, pp. 51-58.
17. W. Shi and Z. Li, "An O(n log n) Time Algorithm for Optimal Buffer Insertion", IEEE/ACM Design Automation Conf., 2003, pp. 580-585.
18. L. P. P. P. van Ginneken, "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay", Intl. Symposium on Circuits and Systems, 1990, pp. 865-868.