New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 395-400

  Lillis, John ^a   Cheng, Chung Kuan ^a   Lin, Ting Ting Y ^a   Ho, Ching Yen ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC VARIABLES CONTROL; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; TREES (MATHEMATICS); VLSI CIRCUITS;

ELMORE DELAY MODEL; PERFORMANCE DRIVEN ROUTING; RECTILINEAR STEINER TREES;

DELAY CIRCUITS;

EID: 0029712263     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240594     Document Type: Conference Paper

References (17)