Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1997, Pages 260-265

  Takahashi, Atsushi ^a   Inoue, Kazunori ^a   Kajitani, Yoji ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC DELAY LINES; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL MODELS; OPTIMIZATION; TREES (MATHEMATICS);

CLOCK TREE ROUTING ALGORITHMS; SEMI SYNCHRONOUS CIRCUITS; SIGNAL DELAY;

TIMING CIRCUITS;

EID: 0031354140     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.1997.643529     Document Type: Conference Paper

References (25)