Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry

IEEE Transactions on Computers

Volumn 45, Issue 9, 1996, Pages 1031-1044

  Linder, Daniel H ^a,b   Harden, James C ^b  

^a IEEE

^b MISSISSIPPI STATE UNIVERSITY   (United States)

Author keywords

Asynchronous circuitry; Data flow; Delay insensitive circuitry; Dual rail encoding; LEDR; Marked graphs; Phased logic; Synchronous circuitry

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED LOGIC DESIGN; DELAY CIRCUITS; GRAPH THEORY; LOGIC GATES; MATHEMATICAL MODELS; PERFORMANCE; PETRI NETS; SIGNAL ENCODING; TIMING CIRCUITS;

ASYNCHRONOUS CIRCUITRY; DATA FLOW; DELAY INSENSITIVE CIRCUITRY; DUAL RAIL ENCODING; LEVEL ENCODED TWO PHASE DUAL RAIL; LOW SKEW CLOCK SIGNALS; MARKED GRAPHS; PHASED LOGIC; PROPAGATION DELAYS; SYNCHRONOUS CIRCUITRY;

LOGIC DESIGN;

EID: 0030244752     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.537126     Document Type: Article

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