A coarse-grain phased logic CPU

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2003, Pages 2-13

  Reese, Robert B ^a   Thornton, Mitchell A ^b   Traver, Cherrice ^c  

^a MISSISSIPPI STATE UNIVERSITY   (United States)

^b SOUTHERN METHODIST UNIVERSITY   (United States)

^c UNION COLLEGE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; FLIP FLOP CIRCUITS;

COARSE GRAINS; CONTROL LOGIC; D FLIP FLOPS; EARLY EVALUATION; IMPLEMENTATION SCHEME; LOGIC BLOCKS; NETLIST; PHASED LOGIC; PIPELINED CPU; SELF-TIMED;

TABLE LOOKUP;

EID: 77957962323     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2003.1199161     Document Type: Conference Paper

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