A system for full-chip and critical net parasitic extraction for ulsi interconnects using a fast 3-D field solver

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 3, 2000, Pages 325-338

  Bächtold, Martin ^a   Spasojevic, Mirko ^a   Lage, Christian ^a   Ljung, Per B ^a  

^a Coyote Systems Inc ^*  (United States)

Author keywords

1c interconnect; Capacitance; Critical net full chip parasitic extraction; Field solver; Meshing

Indexed keywords

CAPACITANCE; COMPUTATIONAL GEOMETRY; COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; INTEGRATED CIRCUIT MANUFACTURE; LSI CIRCUITS; THREE DIMENSIONAL;

DEEP SUBMICRON; INTEGRATED CIRCUIT INTERCONNECT; PARASITIC CAPACITANCE EXTRACTION; THREE DIMENSIONAL FIELD SOLVER; ULTRA LARGE SCALE INTEGRATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034157087     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.833201     Document Type: Article

References (41)

1. N. D. Arora, K. V. Raol, R. Schumann, and L. M. Richardson, "Modeling and extraction of interconnect capacitances for multilayer VLSI circuits," IEEE Trans. Computer-Aided Design, vol. 15, pp. 58-67, Jan. 1996.
2. U. Choudhury and A. Sangiovanni-Vincenteli, "Automatic generation of analytical models for interconnect capacitances," IEEE Trans. Electron Devices, vol. 14, pp. 470-80, Apr. 1995.
3. S. Y. Oh et al., "3-D GIPER: Global interconnect parameter extractor for full-chip global critical path analysis," in IEEE Proc. IEDM, 1996, pp. 615-618.
4. Y. L. Le Coz, R. B. Iverson, H. J. Greub, P. M. Campbell, and J. F. MacDonald, "Application of a floating random-walk algorithm for extracting capacitances in a realistic HBT fast-RISC RAM cell," in Proc. Ilth Int. VLSI Multilevel Interconnection Conf. (VMIC), 1994, pp. 542-544.
5. M. Bächtold, "Efficient 3-D computation of electrostatic fields and forces in microsystems," Ph.D. dissertation, Phys. Electron. Lab., ETH Zurich, Zurich, Switzerland, 1997.
6. A. H. Zemanian, R. P. Tewarson, C. P. Ju, and J. F. Jen, "Three-dimension capacitance computations for VLSI/ULSI interconnections," IEEE Trans. Computer-Aided Design, vol. 8, pp. 1319-1326, Dec. 1989.
7. A. Seidl, M. Svoboda, J. Oberndorfer, and W. Rosner, "CAPCAL-A 3-D capacitance sol ver for support of CAD systems," IEEE Trans. Computer-Aided Design, vol. 7, pp. 549-556, May 1988.
8. R. Martins, W. Pyka, R. Sabelka, and S. Selberherr, "High precision interconnect analysis," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1148-1159, Nov. 1998.
9. M. Mukai, T. Tatsumi, N. Nakauchi, T. Kobayashi, K. Koyama, Y Komatsu, R. Bauer, G. Rieger, and S. Selberherr, "The simulation system for three-dimensional capacitance and current density calculation with a user-friendly GUI," Tech. Rep. IEICE, vol. 95, 1995.
10. A. J. van Genderen and N. P. van der Meijs, "Using articulation nodes to improve the efficiency of finite-element based resistance extraction," in Proc. DAC'96, 1996, pp. 758-763.
11. O. E. Akcasu et al, "NET-AN, a full three-dimensional parasitic interconnect distributed RLC extractor for large full-chip applications," in Proc. IEDM, IEEE, 1995, pp. 495-98.
12. R. Bauer, M. Stiftinger, and S. Selberherr, "Capacitance calculation of VLSI multilevel wiring structures," in Proc. VPAD, 1993, pp. 142-143.
13. Q. Ning, P. M. Dewilde, and F. L. Neerhoff, "Capacitance coefficients for VLSI multilevel metallization lines," IEEE Trans. Electron Devices, vol. ED-34, pp. 644-649, Mar. 1987.
14. K. Nabors and J. White, "FastCap: A multipole-accelerated 3-D capacitance extraction program," IEEE Trans. Computer-Aided Design, vol. 10, pp. 1447-1459, Nov. 1991.
15. Z. Wang, Y Yuan, and Q. Wu, "A parallel multipole accelerated 3-D capacitance simulator based on an improved model," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1441-1450, Dec. 1996.
16. M. Bächtold, J. G. Korvink, and H. Baltes, "Enhanced multipole acceleration technique for the solution of large poisson computations," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1541-1546, Dec. 1996.
17. K. Nabors, J. Phillips, F. T. Korsmeyer, and J. White, "Multipole and precorrected-FFT accelerated iterative methods for solving surface integral formulations of three-dimensional laplace problems," in Proc. Domain-Based Parallelism and Problem Decomposition Methods in Computer Science and Engineering Workshop, 1993.
18. R. H. Uebbing and M. Fukuma, "Process-based three-dimensional capacitance simulation-TRICEPS," IEEE Trans. Computer-Aided Design, vol. CAD5, pp. 215-220, Jan. 1986.
19. J. P. Elliot, G. A. Allan, and A. J. Walton, "The automatic generation of conformai 3-D data for interconnect capacitance simulation," in Proc. VLSI Multi-Level Interconnect Conf., 1995, pp. 664-666.
20. E. W. Scheckler and A. R Neureuther, "Coupling model and algorithms for 3-D topography simulation: Plasma etching, ion milling and deposition in SAMPLE-3-D," in Proc. Workshop on Numerical Models of Processes and Devices for Integrated Circuits, 1992, pp. 9-14.
21. J. Pelka, "Three-dimensional simulation of ion-enhanced dry-etch processes," Microelectron. Eng., vol. 14, pp. 269-281, 1991.
22. E. Strasser and S. Selberherr, "Algorithms and models for cellular based topography simulation," IEEE Trans. Computer-Aided Design, vol. 14, pp. 1104-1114, Sept. 1995.
23. M. Bächtold, M. Emmenegger, J. G. Korvink, and H. Baltes, "An error indicator and automatic adaptive meshing for electrostatic boundary element simulations," IEEE Trans. Computer-Aided Design, vol. 16, pp. 1439-1446, Dec. 1997.
24. M. Bächtold and P. B. Ljung, "The constrained boundary element method, a technique allowing general surface meshes in MEMS simulations," in Tech. Dig. Solid-State Sensor and Actuator Workshop, Hilton Head Island, SC, 1998, pp. 201-204.
25. M. Bächtold, S. Taschini, J. G. Korvink, and H. Baltes, "Automated extraction of capacitances and electrostatic forces in MEMS and ULSI interconnects from the mask layout," in IEEE P roc. IEDM, 1997, pp. 129-132.
26. A. Murta. A Generic Polygon Clipping Library. Online Available: HTTP: http://www.cs.man. ac.uk/aig/staff/alan/software/gpc.html
27. M. Bächtold, J. G. Korvink, and H. Baltes, "An error indicator and automatic adaptive meshing for 3-D electrostatic boundary element simulations," in Boundary Elements XIX. Southampton, U.K.: Comput. Mechanics Publ., 1997, pp. 709-718.
28. Y. Saad and M. Schulz, "GMRES: A generalized minimal residual algorithm for solving nonsymmetric linear systems," SIAM J. Sei. Statist. Comput.. vol. 7, no. 3, pp. 856-869, 1986.
29. M. Bächtold, J. G. Korvink, and H. Baltes, "Automatic adaptive meshing for efficient electrostatic boundary element simulations," in Proc. SISPAD, IEEE. 1996, pp. 127-128.
30. L. Greengard, The Rapid Evaluation of Potential Fields in Particle Systems. Cambridge, MA: MIT Press, 1988.
31. M. Bächtold, M. Emmenegger, S. Taschini, J. Funk, K. Eamboglia, R. Rühl, J. G. Korvink, and H. Baltes, "A CAD system for microsystem simulation," in Proc. MINAST 1st Annu. Conv.. Berne, Switzerland, 1997, pp. 104-105.
32. P. B. Ejung and M. Bächtold, "Automatic model generation and analysis for MEMS," in Proc. ASME'98, 1998.
33. C. A. Brebbia, J. C. F. Telles, and E. C. Wrobel, Boundary Element Techniques, Theory and Application in Engineering. Berlin, Germany: Springer-Verlag, 1984.
34. J. Rubinstein, P. Penfield, and M. A. Horowitz, "Single delay in RC tree networks," IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983.
35. Q. Zhu, W. M. Dai, and J. G. Xi, "Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models," in Proc. Int. Conf. Computer-Aided Design, 1993, pp. 628-633.
36. M. Celik and E. T. Pileggi, "Metrics and bounds for phase delay and signal attenuation in RC(E) clock trees," IEEE Trans. Computer-Aided Design, vol. 18, pp. 293-300, Mar. 1999.
37. A. Deutsch, G. Kopcsay, C. Surovic, B. Rubin, E. Terman, R. Dünne, T. Gallo, and R. Dennard, "Modeling and characterization of long on-chip interconnections for high-performance microprocessors," IBM J. Res. Dev., vol. 39, no. 5, pp. 547-567, 1995.
38. B. Krauter, Y. Xia, A. Dengi, and E. Pileggi, "A sparse image method for BEM capacitance extraction," in Proc. 33rd Design Automation Conf., 1996, pp. 357-362.
39. M. W. Beattie and E. Pileggi, "Error bounds for capacitance extraction via window techniques," IEEE Trans. Computer-Aided Design, vol. 18, pp. 311-321, Mar. 1999.
40. Ch. Eage and Ch. Schwab, "Advanced boundary element algorithms," in Highlights of the MAFELAP X Conference, J. Whiteman, Ed. Amsterdam, The Netherlands: Elsevier, 2000.
41. E. Greengard, The Rapid Evaluation of Potential Fields in Particle Systems. Cambridge, MA: MIT Press, 1988.