Effect of parameter variations at chip and wafer level on clock skews

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 4, 2000, Pages 395-400

  Sauter, Stephan ^b   Schmitt Landsiedel, Doris ^c   Thewes, Roland ^a,b   Weber, Werner ^a,b  

^a IEEE

^b INFINEON TECHNOLOGIES AG   (Germany)

^c TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); CAPACITANCE MEASUREMENT; COMPUTER SIMULATION; ELECTRIC RESISTANCE MEASUREMENT; INTERCONNECTION NETWORKS; SILICON WAFERS; TIMING CIRCUITS;

CLOCK DISTRIBUTION CIRCUITS; CLOCK SKEWS; INTERCONNECT CAPACITANCE; PROCESS VARIATIONS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0034313441     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.892624     Document Type: Article

References (11)

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