Accurate stacking effect macro-modeling of leakage power in sub-100nm circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 165-170

  Yang, Shengqi ^a   Wolf, Wayne ^a   Vijaykrishnan, N ^b   Xie, Yuan ^b   Wang, Wenping ^c  

^a Princeton University   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

^c PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE STACKING EFFECT; LEAKAGE POWER; MACRO-MODEL; TRANSISTOR STACKING;

ERROR ANALYSIS; GATES (TRANSISTOR); MATHEMATICAL MODELS; OPTIMIZATION; VECTORS;

LEAKAGE CURRENTS;

EID: 27944507627     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2005.41     Document Type: Conference Paper

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