Topological analysis for leakage prediction of digital circuits

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 39-44

  Jiang, Wenjie ^a   Tiwari, V ^a   De La Iglesia, E ^b   Sinha, A ^c  

^a INTEL CORPORATION   (United States)

^b Aplatform Internet Service   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; COMPUTER AIDED DESIGN; DESIGN; ESTIMATION; FORECASTING; LEAKAGE CURRENTS; REACTOR CORES; RECONFIGURABLE HARDWARE; TOPOLOGY; VLSI CIRCUITS; VOLTAGE SCALING;

ESTIMATION RESULTS; LEAKAGE ESTIMATION; LEAKAGE REDUCTION; PREDICTION UNCERTAINTY; PRODUCT SPECIFICATIONS; STACKING FACTORS; SUB-THRESHOLD LEAKAGE CURRENTS; TOPOLOGICAL ANALYSIS;

UNCERTAINTY ANALYSIS;

EID: 84962324887     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994882     Document Type: Conference Paper

References (7)

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