Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges

IEEE Region 10 Annual International Conference, Proceedings/TENCON

Volumn D, Issue , 2004, Pages

  Misra, D ^a,b   Choudhury, N A ^a   Garg, R ^a   Srinivasan, P ^a  

^a IEEE   (United States)

^b NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; GATE DIELECTRICS;

DIELECTRIC MATERIALS; FABRICATION; FORECASTING; SILICA;

CMOS INTEGRATED CIRCUITS;

EID: 27944462684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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