-
1
-
-
84861271666
-
-
ARM, ARM Processor Cores. http://www.armdevzone.com/open.nsf/htmlall/ A944EB65693A4E B180256A440051457A/$File/ARM+cores+111-1.pdf
-
ARM Processor Cores
-
-
-
2
-
-
0033722287
-
A minimum total power methodology for projecting limits on CMOS GSI
-
June
-
A. Bhavnagarwala, et al., "A Minimum Total Power Methodology for Projecting Limits on CMOS GSI," IEEE Trans. VLSI Systems, vol. 8, no. 3, June 2000, pp. 235-251.
-
(2000)
IEEE Trans. VLSI Systems
, vol.8
, Issue.3
, pp. 235-251
-
-
Bhavnagarwala, A.1
-
3
-
-
0034315851
-
A dynamic voltage scaled microprocessor system
-
T. Burd, et al., "A Dynamic Voltage Scaled Microprocessor System," in Proc. Int. Solid-State Circuits Conf, vol. 35, no. 11, 2000, pp. 1571-80.
-
(2000)
Proc. Int. Solid-state Circuits Conf
, vol.35
, Issue.11
, pp. 1571-1580
-
-
Burd, T.1
-
6
-
-
0035507074
-
An embedded 32-b microprocessor core for low-power and high-performance applications
-
Nov.
-
L. Clark, et al., "An Embedded 32-b Microprocessor Core for Low-Power and High-Performance Applications," J. Solid-State Circuits, vol. 36, no. 11, Nov. 2001, pp. 1599-1608.
-
(2001)
J. Solid-state Circuits
, vol.36
, Issue.11
, pp. 1599-1608
-
-
Clark, L.1
-
7
-
-
4444292368
-
Faster and lower power cell-based designs with transistor-level cell sizing
-
chapter 9, Kluwer
-
M. Cote, and P. Hurat, "Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing," chapter 9 in Closing the Gap Between ASIC & Custom, Kluwer, 2002.
-
(2002)
Closing the Gap between ASIC & Custom
-
-
Cote, M.1
Hurat, P.2
-
9
-
-
27944480551
-
Data driven VLSI computation for low power DCT-based video coding
-
L. Fanucci, and S. Saponara, "Data driven VLSI computation for low power DCT-based video coding," in Proc. Int. Conf. Electronics, Circuits and Systems, vol.2, 2002, pp. 541-4.
-
(2002)
Proc. Int. Conf. Electronics, Circuits and Systems
, vol.2
, pp. 541-544
-
-
Fanucci, L.1
Saponara, S.2
-
12
-
-
0029701437
-
Simultaneous buffer and wire sizing for performance and power optimization
-
J. Gong, et al., "Simultaneous buffer and wire sizing for performance and power optimization," in Proc. Int. Symp. on Low Power Electronics and Design, 1996, pp. 271-6.
-
(1996)
Proc. Int. Symp. on Low Power Electronics and Design
, pp. 271-276
-
-
Gong, J.1
-
15
-
-
27944504036
-
Samsung twists ARM past 1GHz
-
Oct. 16
-
M. Levy, "Samsung Twists ARM Past 1GHz," Microprocessor Report, Oct. 16, 2002.
-
(2002)
Microprocessor Report
-
-
Levy, M.1
-
16
-
-
0030285348
-
A 160MHz, 32-b, 0.5W, CMOS RISC microprocessor
-
J. Montanaro, et al., "A 160MHz, 32-b, 0.5W, CMOS RISC Microprocessor," J. Solid-State Circuits, vol. 31, no. 11, 1996, pp. 1703-14.
-
(1996)
J. Solid-state Circuits
, vol.31
, Issue.11
, pp. 1703-1714
-
-
Montanaro, J.1
-
17
-
-
0347150009
-
Low-power design for embedded processors
-
Nov.
-
B. Moyer, "Low-Power Design for Embedded Processors," Proc. IEEE, vol. 89, no. 11, Nov. 2001, 1576-1587.
-
(2001)
Proc. IEEE
, vol.89
, Issue.11
, pp. 1576-1587
-
-
Moyer, B.1
-
18
-
-
0034798973
-
Comparative performance, leakage power and switching power of circuits in 150 nm PD-SOI and bulk technologies including impact of SOI history effect
-
S. Narendra, et al., "Comparative Performance, Leakage Power and Switching Power of Circuits in 150 nm PD-SOI and Bulk Technologies Including Impact of SOI History Effect," Int. Symp. on VISI Circuits, 2001, pp. 217-8.
-
(2001)
Int. Symp. on VISI Circuits
, pp. 217-218
-
-
Narendra, S.1
-
21
-
-
0042635592
-
Pushing ASIC performance in a power envelope
-
R. Puri et al., "Pushing ASIC Performance in a Power Envelope," in Proc. Design Automation Conf., 2003, pp. 788-793.
-
(2003)
Proc. Design Automation Conf.
, pp. 788-793
-
-
Puri, R.1
-
23
-
-
84949183533
-
Comparison of bulk and SOI CMOS technologies in a DSP processor circuit implementation
-
P. Simonen, et al., "Comparison of bulk and SOI CMOS Technologies in a DSP Processor Circuit Implementation," in Proc. Int. Conf. Microelectronics, 2001.
-
(2001)
Proc. Int. Conf. Microelectronics
-
-
Simonen, P.1
-
24
-
-
0029292281
-
Power conscious CAD tools and methodologies: A perspective
-
April
-
D. Singh, et al., "Power Conscious CAD Tools and Methodologies: a Perspective," Proc. IEEE, vol. 83, no. 4, April 1995, pp. 570-94.
-
(1995)
Proc. IEEE
, vol.83
, Issue.4
, pp. 570-594
-
-
Singh, D.1
-
25
-
-
0032688692
-
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
-
S. Sirichotiyakul, et al., "Stand-by Power Minimization through Simultaneous Threshold Voltage Selection and Circuit Sizing," in Proc. Design Automation Conf, 1999, pp. 436-41.
-
(1999)
Proc. Design Automation Conf
, pp. 436-441
-
-
Sirichotiyakul, S.1
-
28
-
-
0032205691
-
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme
-
M. Takahashi, et al., "A 60-mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme," J. Solid-State Circuits, vol. 33, no. 11, 1998, pp. 1772-1780.
-
(1998)
J. Solid-state Circuits
, vol.33
, Issue.11
, pp. 1772-1780
-
-
Takahashi, M.1
-
29
-
-
0010893420
-
Low-power design methodology and applications utilizing dual supply voltages
-
K. Usami, and M. Igarishi, "Low-Power Design Methodology and Applications Utilizing Dual Supply Voltages," in Proc. ASP Design Automation Conf, 2000, pp. 123-8.
-
(2000)
Proc. ASP Design Automation Conf
, pp. 123-128
-
-
Usami, K.1
Igarishi, M.2
-
30
-
-
0021477994
-
Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
-
August
-
H. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," J. Solid-State Circuits, vol. SC-19, August 1984, pp. 468-73.
-
(1984)
J. Solid-state Circuits
, vol.SC-19
, pp. 468-473
-
-
Veendrick, H.1
-
31
-
-
84861274691
-
-
Virtual Silicon, http://www.virtual-silicon.com/
-
-
-
-
32
-
-
0000194406
-
A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization
-
May
-
T. Xanthopoulos, and A. Chandrakasan, "A Low-Power DCT Core Using Adaptive Bitwidth and Arithmetic Activity Exploiting Signal Correlations and Quantization," J. Solid-State Circuits, vol. 35, no. 5, May 2000, pp. 740-50.
-
(2000)
J. Solid-state Circuits
, vol.35
, Issue.5
, pp. 740-750
-
-
Xanthopoulos, T.1
Chandrakasan, A.2
-
33
-
-
0032614261
-
A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity
-
May
-
T. Xanthopolous, and A. Chandrakasan, "A Low-Power IDCT Macrocell for MPEG-2 MP@ML Exploiting Data Distribution Properties for Minimal Activity," J. Solid-State Circuits, vol. 34, May 1999, pp. 693-703.
-
(1999)
J. Solid-state Circuits
, vol.34
, pp. 693-703
-
-
Xanthopolous, T.1
Chandrakasan, A.2
|