Gate-level synthesis for low-power using new transformations

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1996, Pages 297-300

  Pradhan, Dhiraj K ^a   Chatterjee, Mitrajit ^a   Swarna, Madhu V ^a   Kunz, Wolfgang ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; POWER ELECTRONICS; PROBABILITY; SWITCHING;

BOOLEAN TRANSFORMATIONS; GATE LEVEL SYNTHESIS; LOGIC OPTIMIZATION; POWER CONSUMPTION; POWER ESTIMATION MODEL; RANDOM PATTERN SIMULATION; SWITCHING ACTIVITY;

LOGIC DESIGN;

EID: 0030399155     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)