Effects of sub-gate bias on the operation of Schottky-barrier SOI MOSFETs having nano-scale channel

Proceedings of the IEEE Conference on Nanotechnology

Volumn 2002-January, Issue , 2002, Pages 205-208

  Lin, Horng Chih ^a   Wang, Meng Fan ^a   Hou, Fu Ju ^a   Liu, Jan Tsai ^a   Li, Yiming ^a   Huang, Tiao Yuan ^a   Sze, S M ^a  

^a NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

Annealing; CMOS process; Contacts; Fabrication; Manufacturing; MOSFETs; Nanoscale devices; Passivation; Silicides; Voltage

Indexed keywords

ANNEALING; BIAS VOLTAGE; CMOS INTEGRATED CIRCUITS; CONTACTS (FLUID MECHANICS); ELECTRIC POTENTIAL; FABRICATION; MANUFACTURE; NANOTECHNOLOGY; PASSIVATION; SCHOTTKY BARRIER DIODES; SILICIDES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

CMOS PROCESSS; MOSFETS; NANOSCALE DEVICE; ON/OFF CURRENT RATIO; SCHOTTKY SOURCE/DRAIN; SILICON ON INSULATOR DEVICES; SUBTHRESHOLD SWING; THRESHOLD VOLTAGE ROLL-OFF;

MOSFET DEVICES;

EID: 0038483204     PISSN: 19449399     EISSN: 19449380     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2002.1032226     Document Type: Conference Paper

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