Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 11, 2005, Pages 1748-1758

  Li, James Chien Mo ^a,b   McCluskey, Edward J ^a,c,d,e,f  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c Stanford University   (United States)

^d STANFORD UNIVERSITY   (United States)

^e Northwestern U   (United States)

^f Center for Reliable Computing   (United States)

Author keywords

Automatic test pattern generation (ATPG); Fault diagnosis; Testing; Very large scale integration (VLSI)

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION (ATPG); CIRCUIT NODES; FAULT DIAGNOSIS; STUCK-OPEN DEFECT;

DEFECTS; ELECTRIC FAULT LOCATION; MICROPROCESSOR CHIPS; RESISTORS; TESTING; VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 27744441772     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.852457     Document Type: Article

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