메뉴 건너뛰기




Volumn 2002-January, Issue , 2002, Pages 187-192

Diagnosis of sequence-dependent chips

Author keywords

Books; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Fault detection; Fault diagnosis; Semiconductor device modeling; Timing; Uncertainty

Indexed keywords

CIRCUIT SIMULATION; COMBINATORIAL CIRCUITS; FAILURE ANALYSIS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; TIMING CIRCUITS; UNCERTAINTY ANALYSIS; VLSI CIRCUITS;

EID: 84948417131     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011137     Document Type: Conference Paper
Times cited : (44)

References (18)
  • 1
    • 0022865883 scopus 로고
    • Efficient Fault simulation of CMOS Circuits with Accurate Models
    • Barzilai, Z., and et. al., "Efficient Fault simulation of CMOS Circuits with Accurate Models," Proc. Int'l Test Conf., pp. 520-529, 1986.
    • (1986) Proc. Int'l Test Conf. , pp. 520-529
    • Barzilai, Z.1
  • 2
    • 0032307602 scopus 로고    scopus 로고
    • Analysis of Pattern-Dependent and Timing Dependent Failure in An Experimental Test Chip
    • Chang, J., et. al., "Analysis of Pattern-Dependent and Timing Dependent Failure in An Experimental Test Chip," Proc. Int'l Test Conf., pp.184-193, 1998.
    • (1998) Proc. Int'l Test Conf. , pp. 184-193
    • Chang, J.1
  • 3
    • 0024122316 scopus 로고
    • Stuck-Open and Transition Fault Testing in CMOS Complex Gates
    • Cox, H. and J. Rajski, "Stuck-Open and Transition Fault Testing in CMOS Complex Gates," Proc. Int. Test Conf., pp.688-694, 1988.
    • (1988) Proc. Int. Test Conf. , pp. 688-694
    • Cox, H.1    Rajski, J.2
  • 12
  • 14
    • 0016080487 scopus 로고
    • Bridging and Stuck-at Faults
    • July
    • Mei K. C. Y., "Bridging and Stuck-at Faults," IEEE Trans. on Comput. Vol. C-23, No. 7, pp. 720-727, July 1974.
    • (1974) IEEE Trans. on Comput. , vol.C-23 , Issue.7 , pp. 720-727
    • Mei, K.C.Y.1
  • 18
    • 0017961684 scopus 로고
    • Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits
    • May-June
    • Wadsack, R.L., " Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits," Bell System Tech. J., Vol. 57, No. 5, pp.1449-1488, May-June, 1978.
    • (1978) Bell System Tech. J. , vol.57 , Issue.5 , pp. 1449-1488
    • Wadsack, R.L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.