Application of novel failure analysis techniques for advanced multi-layered CMOS devices

IEEE International Test Conference (TC)

Volumn , Issue , 1997, Pages 304-309

  Hong, Yeoh Eng ^a   We, Martin Tay Tiong ^a  

^a Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FAILURE ANALYSIS; MICROPROCESSOR CHIPS; PROGRAM ASSEMBLERS;

DESIGN FOR TESTABILITY (DFT);

INTEGRATED CIRCUIT TESTING;

EID: 0031344744     PISSN: 10893539     EISSN: None     Source Type: None    
DOI: 10.1109/TEST.1997.639631     Document Type: Conference Paper

References (4)

1. Y. E. Hong M. Tay A. Kesharvarzi J. Uppal H. Sue The application of novel failure analysis techniques and defect modelling in eliminating short poly end-cap problem in Submicron CMOS devices 22 International Symposium for testing and failure analysis 165 22 International Symposium for testing and failure analysis 1996-Nov
2. D. Vallett An overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics International Test Conference 1996 International Test Conference 1996
3. K. Butler K. Johnson J. Blatt A. Jones J. Saxena Integrating Automated Diagnosis into the testing and failure analysis operations International Test Conference 1996 International Test Conference 1996
4. J. Soden R. Anderson C. Henderson IC Failure Analysis Tools and Techniques-Magic, Mystery, and Science International Test Conference 1996 International Test Conference 1996