A Statistical Study of Defect Maps of Large Area VLSI IC’s

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 2, Issue 2, 1994, Pages 249-256

  Koren, Israel ^a   Koren, Zahava ^a   Stapper, Charles H ^b  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

^b Department of Industrial Engineering and Operations Research University of Massachusetts ^*  (United States)

Author keywords

quality IC ; s medium area clustering model yield models. Defect maps large area clustering model low

Indexed keywords

DEFECTS; GRAPH THEORY; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PERFORMANCE; STATISTICAL METHODS; VLSI CIRCUITS;

BINOMIAL DISTRIBUTION; DEFECT MAP; EMPIRICAL DISTRIBUTION; LARGE AREA CLUSTERING MODEL; LOW QUALITY INTEGRATED CIRCUIT; MEDIUM AREA CLUSTERING MODEL; YIELD MODEL;

WSI CIRCUITS;

EID: 0028454905     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.285750     Document Type: Article

References (8)

1. J. A. Cunningham, “The use and evaluation of yield models in integrated circuit manufacturing,” IEEE Trans. Semiconductor Manufact., vol. 3, no. 2, 60–71, May 1990.
2. J. L. Devore, Probability and Statistics for Engineering and the Sciences. Brooks and Cole, 1990, 3rd ed.
3. J. D. Gibbons, Nonparametric Statistical Inference. Marcel Dekker Inc., 1985, 2nd ed.
4. I. Koren and C. H. Stapper, “Yield models for defect tolerant VLSI circuits: A review,” Defect and Fault Tolerance in VLSI Systems, I. Koren, Ed. New York: Plenum, 1989, pp. 1–21.
5. I. Koren, Z. Koren, and C. H. Stapper, “Analysis of defect maps of large area VLSI ICs,” 1992 IEEE Wkshp. on Defect and Fault Tolerance in VLSI Syst., pp. 267–276, 1992.
6. I. Koren, Z. Koren, and C. H. Stapper, “A unified negative binomial distribution for yield analysis of defect tolerant circuits,” IEEE Trans. Comput., vol. 42, pp. 437-724, June 1993.
7. Z. Koren and I. Koren, “A unified approach for yield analysis of defect tolerant circuits,” Defect and Fault Tolerance in VLSI Syst., C. H. Stapper, V. K. Jain, and G. Saucier, Eds., vol. 2. New York: Plenum, 1990, pp. 33–45.
8. C. H. Stapper, “Small-area fault clusters and fault-tolerance in VLSI circuits,” IBM J. Res. Develop., vol. 33, Mar. 1989.