Analysis and evaluation of multisite testing for VLSI

IEEE Transactions on Instrumentation and Measurement

Volumn 54, Issue 5, 2005, Pages 1770-1778

  Hashempour, Hamidreza ^a   Meyer, Fred J ^b   Lombardi, Fabrizio ^c  

^a LTX Corp   (United States)

^b Wichita State University   (United States)

^c Northeastern University   (United States)

Author keywords

Automatic test equipment (ATE); Built in self test (BIST); Fault coverage; Multisite testing; Yield

Indexed keywords

AUTOMATIC TESTING; BUILT-IN SELF TEST; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

AUTOMATIC TEST EQUIPMENT; DEVICE UNDER TEST; FAULT COVERAGE; MULTISITE TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 27644524670     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2005.855099     Document Type: Article

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