Test time reduction in a manufacturing environment by combining BIST and ATE

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 186-194

  Hashempour, H ^a   Meyer, F J ^a   Lombardi, F ^a  

^a Northeastern University   (United States)

Author keywords

Art; Automatic test equipment; Automatic testing; Built in self test; Circuit faults; Circuit simulation; Circuit testing; Manufacturing automation; Pulp manufacturing; Switches

Indexed keywords

AUTOMATIC TESTING; CIRCUIT SIMULATION; DEFECTS; DESIGN FOR TESTABILITY; ELECTRIC NETWORK ANALYSIS; EQUIPMENT TESTING; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; MANUFACTURE; SWITCHES; VLSI CIRCUITS;

ART; AUTOMATIC TEST EQUIPMENT; CIRCUIT FAULTS; CIRCUIT TESTING; MANUFACTURING AUTOMATION; PULP MANUFACTURING;

BUILT-IN SELF TEST;

EID: 84948989479     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173515     Document Type: Conference Paper

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