Test cost minimization for hybrid BIST

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2000, Pages 283-291

  Jervan, Gert ^a   Peng, Zebo ^a   Ubar, Raimund ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; BUILT-IN SELF TEST; OPTIMIZATION;

COST MINIMIZATION; DETERMINISTICS; HYBRID BIST; OPTIMAL BALANCE; PSEUDO-RANDOM; PSEUDORANDOM TEST; SYSTEMS-ON-CHIP; TEST COST; TEST PATTERN; TESTING SYSTEMS;

SYSTEM-ON-CHIP; INTEGRATED CIRCUIT TESTING;

PSEUDORANDOM TESTS; SYSTEMS ON CHIP (SOC);

EID: 0034509788     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2000.887168     Document Type: Article

References (12)

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