Testing high-speed SoCs using low-speed ATEs

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 133-138

  Nourani, M ^a   Chin, J ^b  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Application specific integrated circuits; Built in self test; Circuit testing; Circuits and systems; Clocks; Costs; Delay; Frequency; Hardware; System testing

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; COMPUTER HARDWARE; COSTS; DELAY CIRCUITS; HARDWARE; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

CIRCUIT TESTING; CIRCUITS AND SYSTEMS; DELAY; FREQUENCY; SYSTEM TESTING;

BUILT-IN SELF TEST;

EID: 0142257777     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011124     Document Type: Conference Paper

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