A comparative study of electrical characteristic on sub-10-nm double-gate MOSFETs

IEEE Transactions on Nanotechnology

Volumn 4, Issue 5, 2005, Pages 645-647

  Li, Yiming ^a   Chou, Hong Mu ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Adaptive computation; Channel length; Density gradient drift diffusion model; Double gate MOSFET; Drain induced barrier height lowering; Numerical simulation; On off current ratio; Quantum correction transport model; Sub 10 nm; Subthreshold swing

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; NANOSTRUCTURED MATERIALS; SILICON; THRESHOLD VOLTAGE;

ADAPTIVE COMPUTATION; CHANNEL LENGTH; DENSITY GRADIENT DRIFT-DIFFUSION MODEL; DOUBLE-GATE MOSFET; DRAIN-INDUCED BARRIER HEIGHT LOWERING; ON/OFF CURRENT RATIO; QUANTUM CORRECTION TRANSPORT MODEL; SUB 10 NM; SUBTHRESHOLD SWING;

MOSFET DEVICES;

EID: 26644442791     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2005.851440     Document Type: Article

References (13)

1. H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M. Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, "Sub-10-nm planar-bulk-CMOS devices using lateral junction control," in Int. Electron Devices Meeting Tech. Dig., Dec. 7-10, 2003, pp. 20.7.1-20.7.4.
2. D. M. Fried, E. J. Nowak, J. Keidzierski, J. S. Duster, and K. T. Komegay, "A fin-type independent-double-gate NFET," in Proc. Device Research Conf., Jun. 23-25, 2003, pp. 45-46.
3. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in Int. Electron Devices Meeting Tech. Dig., Dec. 2002, pp. 251-254.
4. M. Ieong, H.-S. P. Wong, E. Nowak, J. Kedzierski, and E. C. Jones, "High performance double-gate device technology challenges and opportunities," in Proc. Int. Quality Electronic Design Symp., Mar. 18-21, 2002, pp. 492-495.
5. L. Wei, Z. Chen, and K. Roy, "Design and optimization of double-gate SOI MOSFET's for low voltage low power circuits," in Proc. IEEE Int. Silicon-on-Insulator Conf., Oct. 5-8, 1998, pp. 69-70.
6. R. Venugopal, S. Goasguen, S. Datta, and M. S. Lundstrom, "Quantum mechanical analysis of channel access geometry and series resistance in nanoscale transistors," J. Appl. Phys., vol. 92, no. 1, pp. 292-305, Jan. 2004.
7. V. A. Sverdlov, T. J. Walls, and K. K. Likharev, "Nanoscale silicon MOSFETs: A theoretical study," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1926-1033, Sep. 2003.
8. Y. Li, T.-W. Tang, and X. Wang, "Modeling of quantum effects for ultrathin oxide MOS structures with an effective potential," IEEE Tran. Nanotechnol., vol. 1, no. 4, pp. 238-242, Dec. 2002.
9. A. Asenov, A. R. Brown, and J. R. Watling, "Quantum corrections in the simulation of decanano MOSFETs," Solid State Electron., vol. 47, pp. 1141-1145, Jul. 2003.
10. A. R. Brown, A. Asenov, and J. R. Watling, "Intrinsic fluctuations in sub 10-nm double-gate MOSFET's introduced by discreteness of charge and matter" IEEE Trans. Nanotechnol., vol. 1, no. 4, pp. 195-200, Dec. 2002.
11. J. R. Watling, A. R. Brown, and A. Asenov, "Can the density gradient approach describe the source-drain tunnelling in decanano double-gate MOSFETs?." J. Comput. Electron., vol. 1, no. 1-2, pp. 289-293, Jul. 2002.
12. A. Asenov, G. Roy, C. Alexander, A. R. Brown, J. R. Watling, and S. Roy, "Quantum mechanical and transport aspects of resolving discrete charges in nano-CMOS device simulation," in Proc. 4th IEEE Nanotechnology Conf., Sep. 17-19, 2004, pp. TH2_3_2-1-TH2_3_2-3.
13. Y. Li and S. M. Yu, "A two-dimensional quantum transport simulation of nanoscale double-gate MOSFET's using parallel adaptive technique," IEICE Trans. Inform. Syst., vol. E87-D, no. 7, pp. 1751-1758, Jul. 2004.