Design and optimization of double-gate SOI MOSFETs for low voltage low power circuits

IEEE International SOI Conference

Volumn , Issue , 1998, Pages 69-70

  Wei, Liqiong ^a   Chen, Zhanping ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; PARTIAL DIFFERENTIAL EQUATIONS; POWER SUPPLY CIRCUITS; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; VLSI CIRCUITS; VOLTAGE CONTROL;

DOUBLE GATE SILICON-ON-INSULATOR (DGSOI) MOSFETS; FULLY DEPLETED DEVICES; POISSON'S EQUATION;

MOSFET DEVICES;

EID: 0032314536     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)