Low temperature wafer-scale 3D ICs: Technology and characteristics

2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2005, Pages 183-186

  Kim, Sang K Kevin ^a   Tiwari, Sandip ^a  

^a School of Operations Research and Industrial Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; BUTENES; SILICON WAFERS; THERMAL EFFECTS; THICKNESS MEASUREMENT;

BENZOCYCLOBUTENE (BCB); TEMPERATURE BUDGET; WAFER BONDING; WAFER-SCALE TRANSPLANTATION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 25844481019     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502626     Document Type: Conference Paper

References (15)

1. L. Xue et al., "Three-dimensional integration: technology, use, and issues for mixed-signal applications," IEEE Trans. Electron Devices, vol. 50, pp. 601-609, Mar. 2003.
2. S. K. Kim et al., "Low temperature silicon circuit layering for three-dimensional integration" IEEE Int. SOI Conf., pp. 136-138, 2004.
3. D. S. Yu et al., "Three-dimensional metal gate-high k-GOI CMOSFETs on 1-poly-6-metal 0.18 μm Si device," IEEE IEEE Electron Device Lett., vol. 26, pp. 118-120, 2005.
4. S. Pozder et al., "Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform," IEEE Int. Interconnect Technology Conference, pp. 102-104, 2004.
5. J. Burns et al., "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," IEEE Int. Solid-State Circuits Conf., pp. 268-269, 2001.
6. G.W. Neudeck et al., "Novel silicon epitaxy for advanced MOSFET devices," IEDM Tech. Dig., pp. 169-172, 2000.
7. Y. H. Kang et al., "Fabrication and characteristics of novel load PMOS SSTFT (stacked single-crystal thin film transistor) for 3-Dimensional SRAM memory cell," IEEE Int. SOI Conf., pp. 127-129, 2004.
8. K. Warner et al., "An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication," IEEE Int. SOI Conf., pp. 71-72, 2004.
9. C. C. Liu et al., "Heating effects of clock drivers in bulk, SOI, and 3-D CMOS," IEEE Electron Device Lett., vol. 23, pp. 716-718, 2002.
10. M. B. Kleiner et al., "Thermal analysis of vertically integrated circuits," IEDM Tech. Dig., pp. 487-490, 1995.
11. A. Rahman, et al., "Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)," IEEE Int. Interconnect Technology Conference, pp. 157-159, 2001.
12. J. W. Joyner et al., "Impact of three-dimensional architectures on interconnects in gigascale integration," IEEE Trans. VLSI Systems, vol. 9, pp. 922-928, 2001.
13. S. K. K. Kim et al., "Crosstalk attenuation with ground plane structures in three-dimensionally integrated mixed signal systems," to be presented, IEEE Int. Microwave Symposium (MTT-S), June 2005.
14. S. K. K. Kim et al., "Crosstalk reduction in mixed signal three-dimensionally integrated circuits with inter-device layer ground planes," in press, IEEE Trans. Electron Devices, July, 2005.
15. F. Niklaus et al., "Low-temperature full wafer adhesive bonding," J. Micromech. Microeng., 11, pp. 100-107, 2001.