메뉴 건너뛰기




Volumn 22, Issue 2, 2004, Pages 214-280

A general framework for prefetch scheduling in linked data structures and its application to multi-chain prefetching

Author keywords

Data prefetching; Memory parallelism; Pointer chasing code

Indexed keywords

DATA PREFETCHING; LINKED DATA STRUCTURES (LDS); MEMORY PARALLELISM; MULTIPLE INDEPENDENT POINTER CHAINS; POINTER-CHAISING CODE;

EID: 2542441690     PISSN: 07342071     EISSN: None     Source Type: Journal    
DOI: 10.1145/986533.986536     Document Type: Article
Times cited : (15)

References (39)
  • 2
    • 0003465202 scopus 로고    scopus 로고
    • The SimpleScalar tool set, version 2.0
    • University of Wisconsin-Madison, Madison, WI
    • BURGER, D. AND AUSTIN, T. M. 1997. The SimpleScalar tool set, version 2.0. Tech. rep. CS TR 1342, University of Wisconsin-Madison, Madison, WI.
    • (1997) Tech. Rep. , vol.CS TR 1342
    • Burger, D.1    Austin, T.M.2
  • 4
    • 0003758490 scopus 로고
    • Generalized correlation based hardware prefetching
    • CHARNEY, M. J. AND REEVES, A. P. 1995. Generalized correlation based hardware prefetching. Tech. rep. EE CEG 95-100.
    • (1995) Tech. Rep. , vol.EE CEG 95-100
    • Charney, M.J.1    Reeves, A.P.2
  • 5
    • 0029511258 scopus 로고
    • An effective programmable prefetch engine for on-chip caches
    • Ann Arbor, MI. IEEE Computer Society Press, Los Alamitos, CA
    • CHEN, T.-F. 1995. An effective programmable prefetch engine for on-chip caches. In Proceedings of the 28th Annual Symposium on Microarchitecture (Ann Arbor, MI). IEEE Computer Society Press, Los Alamitos, CA, 237-242.
    • (1995) Proceedings of the 28th Annual Symposium on Microarchitecture , pp. 237-242
    • Chen, T.-F.1
  • 6
    • 0029308368 scopus 로고
    • Effective hardware-based data prefetching for high-performance processors
    • CHEN, T.-F. AND BAER, J.-L. 1995. Effective hardware-based data prefetching for high-performance processors. ACM Trans. Comput. 44, 5 (May), 609-623.
    • (1995) ACM Trans. Comput. , vol.44 , Issue.5 MAY , pp. 609-623
    • Chen, T.-F.1    Baer, J.-L.2
  • 7
    • 0028757333 scopus 로고
    • Sunder: A programmable hardware prefetch architecture for numerical loops
    • ACM Press, New York, NY
    • CHIUEH, T. 1994. Sunder: A programmable hardware prefetch architecture for numerical loops. In Proceedings of Supercomputing '94. ACM Press, New York, NY, 488-497.
    • (1994) Proceedings of Supercomputing '94 , pp. 488-497
    • Chiueh, T.1
  • 14
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • Seattle, WA. ACM Press, New York, NY
    • JOUPPI, N. P. 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture (Seattle, WA). ACM Press, New York, NY, 364-373.
    • (1990) Proceedings of the 17th Annual International Symposium on Computer Architecture , pp. 364-373
    • Jouppi, N.P.1
  • 19
    • 0019892368 scopus 로고
    • Lockup-free instruction fetch/prefetch cache organization
    • Barcelona, Spain. ACM Press, New York, NY
    • KROFT, D. 1981. Lockup-free instruction fetch/prefetch cache organization. In Proceedings of 8th International Symposium on Computer Architecture (Barcelona, Spain). ACM Press, New York, NY, 81-87.
    • (1981) Proceedings of 8th International Symposium on Computer Architecture , pp. 81-87
    • Kroft, D.1
  • 21
    • 0034839064 scopus 로고    scopus 로고
    • Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
    • Goteborg, Sweden. ACM Press, New York, NY
    • LUK, C.-K. 2001. Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors. In Proceedings of the 28th Annual International Symposium on Computer Architecture (Goteborg, Sweden). ACM Press, New York, NY.
    • (2001) Proceedings of the 28th Annual International Symposium on Computer Architecture
    • Luk, C.-K.1
  • 24
    • 0029723172 scopus 로고    scopus 로고
    • Examination of a memory access classification scheme for pointer-intensive and numeric programs
    • Philadelphia, PA. ACM Press, New York, NY
    • MEHROTRA, S. AND HARRISON, L. 1996. Examination of a memory access classification scheme for pointer-intensive and numeric programs. In Proceedings of the 10th ACM International Conference on Supercomputing (Philadelphia, PA). ACM Press, New York, NY.
    • (1996) Proceedings of the 10th ACM International Conference on Supercomputing
    • Mehrotra, S.1    Harrison, L.2
  • 26
    • 0031988272 scopus 로고    scopus 로고
    • Tolerating latency in multiprocessors through compiler-inserted prefetching
    • MOWRY, T. 1998. Tolerating latency in multiprocessors through compiler-inserted prefetching. ACM Trans. Comput. Syst. 16, 1 (Feb.), 55-92.
    • (1998) ACM Trans. Comput. Syst. , vol.16 , Issue.1 FEB. , pp. 55-92
    • Mowry, T.1
  • 27
    • 0002031606 scopus 로고
    • Tolerating latency through software-controlled prefetching in shared-memory multiprocessors
    • MOWRY, T. AND GUPTA, A. 1991. Tolerating latency through software-controlled prefetching in shared-memory multiprocessors. J. Parallel Distrib. Comput. 12, 2 (June), 87-106.
    • (1991) J. Parallel Distrib. Comput. , vol.12 , Issue.2 JUNE , pp. 87-106
    • Mowry, T.1    Gupta, A.2
  • 28
    • 0033356548 scopus 로고    scopus 로고
    • Code transformations to improve memory parallelism
    • Haifa, Israel. IEEE Computer Society Press, Los Alamitos, CA
    • PAI, V. S. AND ADVE, S. 1999. Code transformations to improve memory parallelism. In Proceedings of the International Symposium on Microarchitecture (Haifa, Israel). IEEE Computer Society Press, Los Alamitos, CA.
    • (1999) Proceedings of the International Symposium on Microarchitecture
    • Pai, V.S.1    Adve, S.2
  • 30
    • 0029273301 scopus 로고
    • Supporting dynamic data structures on distributed memory machines
    • ROGERS, A., CARLISLE, M., REPPY, J., AND HENDREN, L. 1995. Supporting dynamic data structures on distributed memory machines. ACM Trans. Programm. Lang. Syst. 17, 2 (March), 233-263.
    • (1995) ACM Trans. Programm. Lang. Syst. , vol.17 , Issue.2 MARCH , pp. 233-263
    • Rogers, A.1    Carlisle, M.2    Reppy, J.3    Hendren, L.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.