A highly fault tolerant PLA architecture for failure-prone nanometer CMOS and novel quantum device technologies

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2004, Pages 39-47

  Schmid, Alexandre ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT-TOLERANCE; FOUR-LAYER STRUCTURES; QUANTUM STRUCTURES; SYSTEM ARCHITECTURE;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FAILURE ANALYSIS; LOGIC CIRCUITS; NANOTECHNOLOGY;

QUANTUM ELECTRONICS;

EID: 24944452442     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347823     Document Type: Conference Paper

References (8)

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