Single electron encoded latches and flip-flops

IEEE Transactions on Nanotechnology

Volumn 3, Issue 2, 2004, Pages 237-248

  Lageweg, Casper ^a   Coţofanǎ, Sorin ^a   Vassiliadis, Stamatis ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Coulomb blockage; Digital circuits; Logic circuits; Single electron tunneling (SET); Threshold logic circuits

Indexed keywords

BOOLEAN ALGEBRA; DIGITAL CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRON TRANSPORT PROPERTIES; ELECTRON TUNNELING; FLIP FLOP CIRCUITS; LOGIC GATES; MOS DEVICES; THRESHOLD ELEMENTS;

COULOMB BLOCKAGE; MEMORY ELEMENTS; SINGLE ELECTRON TUNNELING (SET); THRESHOLD LOGIC CIRCUITS;

NANOTECHNOLOGY;

EID: 2942750315     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2004.828526     Document Type: Article

References (28)

1. Y. Taur, D. A. Buchanan, W. Chen, D. Frank, K. Ismail, S. Lo, G. Sai-Halasz, R. Viswanathan, H. Wann, S. Wind, and H. Wong, "CMOS scaling into the nanometer regime," Proc. IEEE, vol. 85, pp. 486-504, Apr. 1997.
2. A. Korotkov, "Single-electron logic and memory devices," Int. J. Electron., vol. 86, no. 5, pp. 511-547, 1999.
3. K. Likharev, "Single-electron devices and their applications," Proc. IEEE, vol. 87, pp. 606-632, Apr. 1999.
4. "Technology roadmap for nanoelectronics,", [Online]. Available: http://www.cordis.lu/esprit/src/melna-rm.htm, published on the Internet by the Microelectronics Advanced Research Initiative (MELARI NANO), a European Commission (EC) Information Society Technologies (IST) program on Future and Emerging Technologies, 1999.
5. A. Korotkov, R. Chen, and K. Likharev, "Possible performance of capacitively coupled single-electron transistors in digital circuits," J. Appl. Phys., vol. 78, pp. 2520-2530, Aug. 1995.
6. J. R. Tucker, "Complementary digital logic based on the "Coulomb blockade"," J. Appl. Phys., vol. 72, no. 9, pp. 4399-4413, Nov. 1992.
7. K. K. Likharev and V. Semenov, "Possible logic circuits based on the correlated single-electron tunneling in ultrasmall junctions," in Int. Superconductive Conf. Extended Abstracts, 1987, p. 182.
8. Y. N. Nazarov and S. V. Vyshenskii, "SET circuits for digital applications," in Single-Electron Tunneling and Mesoscopic Devices. ser. Electron. Photon., H. Koch and H. Lubbig, Eds. Berlin, Germany: Springer-Verlag, 1992, vol. 31, pp. 61-66.
9. A. Korotkov and K. Likharev, "Single-electron-parametron-based logic devices," J. Appl. Phys., vol. 84, no. 11, pp. 6114-6126, Dec. 1998.
10. C. Wasshuber, H. Kosina, and S. Selberherr, "SIMON - A simulator for single-electron tunnel devices and circuits," IEEE Trans. Computer-Aided Design, vol. 16, pp. 937-944, Sept. 1997.
11. C. Wasshuber, "About single-electron devices and circuits," Ph.D. dissertation, Elect. Eng. Dept., Tech. Univ. Vienna, Vienna, Austria, 1998.
12. D. V. Averin and A. A. Odintsov, "Macroscopic quantum tunneling of the electric charge in small tunnel junctions," Phys. Lett. A, vol. 140, no. 5, pp. 251-257, Sept. 1989.
13. D. V. Averin and Y. V. Nazarov, "Virtual electron diffusion during quantum tunneling of the electric charge," Phys. Rev. Lett., vol. 65, no. 19, pp. 2446-2449, Nov. 1990.
14. S. V. Lotkhov, H. Zangerle, A. B. Zorin, and J. Niemeyer, "Storage capabilities of a four-junction single-electron trap with an on-chip resistor," Appl. Phys. Lett., vol. 75, no. 17, pp. 2665-2667, Oct. 1999.
15. A. B. Zorin, S. V. Lotkhov, H. Zangerle, and J. Niemeyer, "Coulomb blockade and cotunneling in single electron circuits with on-chip resistors: Toward the implementation of the R pump," J. Appl. Phys., vol. 88, no. 5, pp. 2665-2670, Sept. 2000.
16. S. V. Lotkhov, S. A. Bogoslovsky, A. B. Zorin, and J. Niemeyer, "Operation of a three-junction single-electron pump with on-chip resistors," Appl. Phys. Lett., vol. 78, no. 7, pp. 946-948, Feb. 2001.
17. R. Katz, Contemporary Logic Design. Redwood City, CA: Benjamin/Cummings, 1994.
18. J. Wakerly, Digital Design: Principles and Practices, 3rd ed. Upper Saddle River, NJ: Prentice-Hall, 2001.
19. C. Lageweg, S. Coţfanǎ, and S. Vassiliadis, "A linear threshold gate implementation in single electron technology," in IEEE Computer Society VLSI Workshop, Apr. 2001, pp. 93-98.
20. _, "Static buffered SET based logic gates," in 2nd IEEE Nanotechnology Conf., Aug. 2002, pp. 491-494.
21. S. Muroga, Threshold Logic and Its Applications. New York: Wiley, 1971.
22. T. Oya, T. Asai, T. Asai, T. Fukui, and Y. Amemiya, "A majority-logic device using and irreversible single-electron box," IEEE Trans. Nanotechnol., vol. 2, pp. 15-22, Mar. 2003.
23. S. Banerjee, S. Huang, and S. Oda, "Operation of nanocrystalline-silicon-based few-electron memory devices in the light of electron storage, ejection and lifetime characteristics," IEEE Trans. Nanotechnol., vol. 2, pp. 88-92. June 2003.
24. K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai, T. Hashimoto, T. Kobayashi, T. Kure, and K. Seki, "Single-electron memory for giga-to-tera bit storage," Proc. IEEE, vol. 87, pp. 633-651, Apr. 1999.
25. L. Guo, E. Leobandung, and S. Chou, "A silicon single-electron transistor memory operating at room temperature," Science, vol. 275, pp. 649-651, 1997.
26. I. Karafyllidis, "Design and simulation of a single-electron random-access memory array," IEEE Trans. Circuits Syst. I, vol. 49, pp. 1370-1375, Sept. 2002.
27. Z. Durrani, A. Irvine, and H. Aim "Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells," IEEE Trans. Electron Devices, vol. 47. pp. 2334-2339, Dec. 2000.
28. K. Katayama, H. Mizuta, H. Muller, D. Williams, and K. Nakazato. "Design and analysis of high-speed random access memory with coulomb blockade charge confinement," IEEE Trans. Electron Devices, vol. 46, pp. 2210-2216, Nov. 1999.