Buffered Steiner trees for difficult instances

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2001, Pages 4-9

  Alpert, C J ^a   Hrkic, M ^a   Hu, J ^a   Kahng, A B ^a   Lillis, J ^a   Liu, B ^a   Quay, S T ^a   Sapatnekar, S S ^a   Sullivan, A J ^a   Villarrubia, P ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; OPTIMIZATION;

STEINER TREES;

TREES (MATHEMATICS);

EID: 0034832739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/369691.369699     Document Type: Conference Paper

References (13)

1. Wire segmenting for improved buffer insertion
2. Buffer insertion with accurate gate and interconnect delay computation
3. Prim-dijkstra tradeoffs for improved performance-driven routing tree design
4. Near-optimal critical sink routing tree constructions
5. Closed form solution to simultaneous buffer insertion/sizing and wire sizing
6. Performance-driven interconnect design based on distributed RC delay mode
7. Clustering to minimize the maximum inter-cluster distance
8. Maze routing with buffer insertion and wiresizing
9. New performance driven routing techniques with explicit area/ delay tradeoff and simultaneous wire sizing
10. Optimal wire sizing and buffer insertion for low power and a generalized delay model
11. Simultaneous routing and buffer insertion for high performance interconnect
12. Buffered Steiner tree construction with wire sizing for interconnect layout optimization
13. Buffer placement in distributed RC-tree networks for minimal Elmore delay