Simultaneous routing and buffer insertion with restrictions on buffer locations

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 96-99

  Zhou, Hai ^a   Wong, D F ^a   Liu, I Min ^a   Aziz, Adnan ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS; POLYNOMIALS;

MINIMUM ELMORE DELAY; POLYNOMIAL TIME EXACT ALGORITHMS;

VLSI CIRCUITS;

EID: 0032668895     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/309847.309885     Document Type: Conference Paper

References (11)