Multilevel differential encoding with precentering for high-speed parallel link transceiver

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 8, 2005, Pages 1688-1694

  Sim, Jae Yoon ^a   Namgoong, Won ^b  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

^b University of Southern California   (United States)

Author keywords

Circuit noise; Driver circuits; Multilevel encoding; Parallel links, transceivers

Indexed keywords

CIRCUIT NOISE; DRIVER CIRCUITS; MULTILEVEL ENCODING; PARALLEL LINKS;

CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; ELECTRIC CURRENTS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PULSE AMPLITUDE MODULATION; SIGNAL ENCODING; TELECOMMUNICATION LINKS;

TRANSCEIVERS;

EID: 23744496925     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.852010     Document Type: Article

References (22)

1. S. Jou, S. Kuo, J. Chiu, and T. Lin, "Low switching noise and load-adaptive output buffer design techniques," IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1239-1249, Aug. 2001.
2. R. Senthinathan and J. L. Prince, "Application specifie CMOS output driver circuit design techniques to reduce simultaneous switching noise," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1383-1388, Dec. 1993.
3. C. S. Choy, M. H. Ku, and C. F. Chan, "A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 913-917, Jun. 1997.
4. Y. Morooka, Y. Nakase, J.-M. Choi, Y. Shin, D. Perlman, D. Kolor, T. Yoshimura, N. Watanabe, Y. Matsuda, M. Kumanoya, and M. Yamada, "Source synchronization and timing vernier techniques for 1.2 GB/s SL-DRAM interface," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1998, pp. 160-161.
5. T. Sato, Y. Nishio, T. Sugano, and Y. Nakagome, "5 Gbytes data transfer scheme with bit-to-bit skew control for synchronous DRAM," in Symp. VLSI Circuits Dig. Tech. Papers, 1998, pp. 64-65.
6. T. Kirihata, G. Mueller, M. Clinton, S. Loeffler, B. Ji, H. Terletzki, D. Hanson, C. Hwang, G. Lehmann, D. Storaska, G. Daniel, L. Hsu, O. Weinfurtner, T. Boehler, J. Schnell, G. Frankowsky, D. Netis, J. Ross, A. Reith, O. Kiehl, and M. Wordeman, "A 113 mm2 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 382-383.
7. C. Yoo, K. Kyung, K. Lim, H. Lee, J. Chai, N. Heo, D. Lee, and C. Kim, "A 1.8-V 700-Mb/s/pin 512-Mb DDR-II SDRAM with on-die termination and off-chip driver calibration," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 941-951, Jun. 2004.
8. T. Matano, Y. Takai, T. Takahashi, Y. Sakito, I. Fujii, Y. Takaishi, H. Fujisawa, S. Kubouch, S. Narui, K. Arai, M. Morino, M. Nakamura, S. Miyatake, T. Sekiguchi, and K. Koyama, "A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 762-768, Jun. 2003.
9. B. Lau, Y. Chan, A. Moncayo, J. Ho, M. Alien, J. Salmon, J. Liu, M. Muthal, C. Lee, T. Nguyen, B. Horine, M. Leddige, K. Huang, J. Wei, L. Yu, R. Tarver, Y. Hsia, R. Vu, E. Tsern, H. Liaw, J. Hudson, D. Nguyen, K. Donnelly, and R. Crisp, "A 2.6-Gbyte/s multipurpose chip-to-chip interface," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1617-1626, Nov. 1998.
10. E. Reese, H. Wilson, D. Nedwek, J. Jex, M. Khaira, T. Burton, P. Nag, H. Kumar, C. Dike, D. Finan, and M. Haycock, "A phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1994, pp. 296-297.
11. S. Sidiropoulos and M. Horowitz, "A 700 Mb/s/pin CMOS signaling interface using current integrating receivers," IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 681-690, May 1997.
12. H. Song, S. Jang, J. Kwak, C. Kim, C. Kang, D. Jeong, Y. Park, M. Park, K. Byun, W. Lee, Y. Cho, W. Shin, Y. Jang, S. Hwang, Y. Jun, and S. Cho, "A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 314-496.
13. H. Pilo, D. Anand, J. Earth, S. Bums, P. Corson, J. Covino, R. Houghton, and S. Lamphier, "A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 308-495.
14. U. Cho, T. Kim, Y. Yoon, J. Lee, D. Bae, N. Kim, K. Kim, Y. Son, J. Yang, K. Sohn, S. Kim, I. Lee, K. Lee, T. Kang, S. Kim, K. Ahn, and H. Byun, "A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 300-494.
15. J. Zerbe, P. Chau, C. Werner, T. Thrush, H. Liaw, B. Garlepp, and K. Donnelly, "1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 752-760, May 2001.
16. E. Yeung and M. Horowitz, "A 2.4 Gb/s/pin simultaneous bi-directional parallel link with per-pin skew compensation," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1619-1627, Nov. 2000.
17. P. Sotiriadis and A. Chandrakasan, "Bus energy reduction by transition pattern coding using a detailed deep submicrometer bus model," IEEE Trans. Circuits Syst. I, Analog Digit. Signal Process., vol. 50, no. 10, pp. 1280-1295, Oct. 2003.
18. M. Stan and W. Burleson, "Low-power encodings for global communication in cmos VLSI," IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 5, no. 12, pp. 49-58, Dec. 1997.
19. J. Poulton, S. Tell, and R. Palmer, "Methods and systems for transmitting and receiving differential signals over a plurality of conductors," U.S. Patent 6,556,628, Apr. 29, 2003.
20. R. Farjad-Rad, K. Yang, and M. Horowitz, "A 0.3-m CMOS 8-Gb/s 4-PAM serial link transceiver," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 757-764, May 2000.
21. J. Zerbe, C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara, M. Horowitz, and K. Donnelly, "Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2121-2130, Dec. 2003.
22. J. Stonick, G.-Y. Wei, J. Sonntag, and D. Weinlader, "An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25 um CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 436-443, Mar. 2003.