A 1.2Gb/s/spin double data rate SDRAM with on-die-termination

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Song, Ho Young ^a   Jang, Seong Jin ^a   Kwak, Jin Seok ^a   Kim, Cheol Su ^a   Kang, Chang Man ^a   Jeong, Dae Hyun ^a   Park, Yun Sik ^a   Park, Min Sang ^a   Byun, Kyoung Su ^a   Lee, Woo Jin ^a   Cho, Young Cheol ^a   Shin, Won Hwa ^a   Jang, Young Uk ^a   Hwang, Seok Won ^a   Jun, Young Hyun ^a   Cho, Soo In ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC RESISTANCE MEASUREMENT; ERROR COMPENSATION; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; POLYSILICON; RESISTORS; SEMICONDUCTOR QUANTUM WELLS; STATIC RANDOM ACCESS STORAGE; TRANSMISSION LINE THEORY; VOLTAGE REGULATORS;

COLUMN SELECT LINE; DIGITALLY SELF CALIBRATED ON DIE TERMINATION; DOUBLE DATA RATE; STATIC RANDOM ACCESS MEMORY; TERMINATION CIRCUITS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0037630804     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. H.B. Bakoglu, "Circuits, Interconnections, and Packaging for VLSI," Addison-Wesley, 1990.
2. S.Kim, et al., "An 800Mbps Multi-Channel CMOS Serial Link with 3x Oversampling," IEEE CICC Tech. Dig. Papers, pp 451-454, 1995.
3. Gijung Ahn, et al., "A 2-Gbaud 0.7-V Swing Voltage-Mode Driver and On-Chip Terminator for High-Speed NRZ Data Transmission," IEEE, J. Solid-State Circuits, vol. 35, June 2000.
4. W. Dally, "Digital Systems Engineering," Cambridge 1998. pp 477-480.