1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 5, 2001, Pages 752-760

  Zerbe, Jared L ^a,b   Chau, Pak S ^a,b   Werner, Carl W ^a,b   Thrush, Timothy P ^b   Liaw, H J ^a,b   Garlepp, Bruno W ^a,c   Donnelly, Kevin S ^a,b  

^a IEEE   (United States)

^b RAMBUS INC   (United States)

^c SILICON LABORATORIES   (United States)

Author keywords

Integrating receivers; Multilevel systems; Parallel link; Pulse amplititude modulation; Receivers

Indexed keywords

INTEGRATING INPUT RECEIVERS; MULTIDROP SIGNALING SYSTEM; PSEUDORANDOM BIT SEQUENCE;

BANDWIDTH; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; PULSE AMPLITUDE MODULATION; SIGNAL RECEIVERS; SIGNAL TO NOISE RATIO;

CMOS INTEGRATED CIRCUITS;

EID: 0035335623     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.918912     Document Type: Article

References (9)

1. A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver
2. A 2.4-Gb/s per pin simultaneous bidirectional parallel link with per-pin skew calibration
3. A gigabit transceiver chip set for UTP CAT-6 cables in digital CMOS technology
4. A CMOS transceiver for 10 Mb/s and 100 Mb/s ethernet
5. A multiple vendor 2.5-V DLL for 1.6-GB/s RDRAMs
6. A 2.5 V CMOS delay-locked loop for an 18-Mb 500-Mbyte/s DRAM
7. A 700-Mb/s/pin CMOS signaling interface using current integrating receivers
8. Bus design and analysis at 500 MHz and beyond
9. A 2.6-Gbyte/s multipurpose chip-to-chip interface