Low switching noise and load-adaptive output buffer design techniques

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 8, 2001, Pages 1239-1249

  Jou, Shyh Jye ^a   Kuo, Shu Hua ^a   Chiu, Jui Ta ^a   Lin, Tin Hao ^b  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b FARADAY TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

Buffer; Load adaptive; Noise

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC LOADS; FEEDBACK; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SPURIOUS SIGNAL NOISE; SWITCHING;

SWITCHING NOISE;

BUFFER CIRCUITS;

EID: 0035429481     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.938374     Document Type: Article

References (15)

1. Simultaneous switching noise analysis and low bouncing buffer design
2. Simultaneous switching ground noise calculation for packaged CMOS device
3. Effects of CMOS driver loading conditions on simultaneous switching noise
4. Accurate simultaneous switching noise estimation including velocity-saturation effects
5. Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time considerations
6. Effects of simultaneous switching noise on the tapered buffer design
7. Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise
8. Estimation of ground bounce effects on CMOS circuits
9. Adaptive AC/DC output buffer with reduced ground bounce and output ringing
10. Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers
11. Current control buffer for multi switching CMOS SOG
12. Controlled slew rate output buffer
13. Design procedure of low-noise high-speed adaptive output drivers
14. Output buffer with self-adjusting slew rate and on-chip compensation