A 2.6-GByte/s multipurpose chip-to-chip interface

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1617-1624

  Lau, Benedict ^a,c,d,n   Chan, Yiu Fai ^{a,c,e,f,g,h,n}   Moncayo, Alfredo ^a,i,j   Ho, John ^a,g,k,l,m   Allen, Mike ^b   Salmon, Joe ^b   Liu, Jonathan ^b   Muthal, Manish ^b   Lee, Cliff ^b   Nguyen, Tim ^b   Horine, Bryce ^b   Leddige, Mike ^b   Huang, Kuojim ^a   Wei, Jason ^a   Yu, Leung ^a   Tarver, Richard ^a   Hsia, Yuwen ^a   Vu, Roxanne ^a   Tsern, Ely ^a   Liaw, Haw Jyh ^a   Hudson, Jim ^a   Nguyen, David ^a   Donnelly, Kevin ^a   Crisp, Richard ^a,n   more..

^a RAMBUS INC   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d Xicor Inc   (United States)

^e SANTA CLARA UNIVERSITY   (United States)

^f INTERSIL CORPORATION   (United States)

^g ALTERA CORPORATION   (United States)

^h Altera Corp ^*  (United States)

ⁱ STANFORD UNIVERSITY   (United States)

^j HEWLETT PACKARD COMPANY   (United States)

^k SOOCHOW UNIVERSITY   (Taiwan)

^l UNIVERSITY OF MISSOURI   (United States)

^m Teta MicroSystems Inc   (United States)

ⁿ IEEE   (United States)

more..

Author keywords

Clock distribution; CMOS analog circuit; Delay locked loop; DRAM; High speed I O circuits; Signalling; System design

Indexed keywords

CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; LOGIC CIRCUITS; PRINTED CIRCUIT BOARDS;

DELAY LOCKED LOOPS; INPUT/OUTPUT CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 0032202850     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726545     Document Type: Article

References (5)

1. T. Lee et al., "A 2.5 V CMOS delay-locked loop for an 18 Mbit, 500 megabytes/s DRAM," IEEE J. Solid-State Circuits, vol. 29, pp. 1491-1496, Dec. 1994.
2. R. Crisp et al., "Development of Single-chip multi-GB/s DRAM's," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 226-227.
3. M. Griffin et al., "A process-independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory" in ISSCC Dig. Tech. Papers, Feb. 1998, pp. 156-157.
4. K Donnelly et al. "A 660MB/s interface megacell portable circuit in 0.3-0.7 μm CMOS ASIC," IEEE J. Solid-State Circuits, vol. 31, pp. 1995-2003, Dec. 1996.
5. A. Moncayo et al. "Bus design and analysis at 500 MHz and beyond," presented at the Design SuperCon, 1995.