A 5.6ns random cycle 144Mb DRAM with 1.4Gb/s/pin and DDR3-SRAM interface

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Pilo, Harold ^a   Anand, Darren ^a   Barth, John ^a   Burns, Steve ^a   Corson, Phil ^a   Covino, Jim ^a   Houghton, Russ ^a   Lamphier, Steve ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CHARGE TRANSFER; DECODING; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; LOGIC DESIGN; LOGIC GATES; STATIC RANDOM ACCESS STORAGE;

DOUBLE DATA RATE; DYNAMIC PRECHARGE SCHEME; EARLY WRITE SENSING TECHNIQUE; STATIC RANDOM ACCESS MEMORY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0037630805     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Klee, V., et al., "A 0.13μm Logic-Based Embedded DRAM Technology with Electrical Fuses, Cu Interconnect in SiLKTM, Sub-7ns Random Access Time and its Extension to the 0.10mm Generation," Proceedings of IEDM, pp. 407-410, 2001.
2. Pilo, H., et al., "An 833MHz 1.5W 18Mb CMOS SRAM with 1.67Gb/s/pin," ISSCC Digest of Technical Papers, pp. 266-267, 2000.
3. Barth, J., et al., "A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-line Twisting and Direct Reference Cell Write," ISSCC Digest of Technical Papers, pp. 156-157, 2002.
4. Agata, Y. et al., "An 8ns Random Cycle Embedded RAM Macro with Dual-Port Interleaved DRAM Architecture (D2RAM)," ISSCC Digest of Technical Papers, pp. 392-393, 2000.