Source synchronization and timing vernier techniques for 1.2 GB/s SLDRAM interface

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 160-161,-431

  Morooka, Yoshikazu ^a   Nakase, Yasunobu ^a   Choi, Jae Myoung ^a   Shin, Hyun J ^a   Perlman, David J ^a   Kolor, Daniel J ^a   Yoshimura, Tsutomu ^a   Watanabe, Naoya ^a   Matsuda, Yoshio ^a   Kumanoya, Masaki ^a   Yamada, Michihiro ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA TRANSFER; ELECTRONICS PACKAGING; PRINTED CIRCUIT BOARDS; SYNCHRONIZATION; TIMING CIRCUITS;

DYNAMIC RANDOM ACCESS MEMORY (DRAM); TIMING VERNIER TECHNIQUES;

RANDOM ACCESS STORAGE;

EID: 0031652004     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)