Can SAT be used to improve sequential ATPG methods ?

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 585-590

  Prasad, Mukul R ^a   Hsiao, Michael S ^b   Jain, Jawahar ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL EQUIVALENCE CHECKING; DESIGN VERIFICATION; ITERATIVE LOGIC ARRAY (ILA);

ASYNCHRONOUS SEQUENTIAL LOGIC; BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; GENETIC ALGORITHMS; PROBLEM SOLVING; THEOREM PROVING; VECTORS;

INTEGRATING CIRCUITS;

EID: 2342586655     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (33)

1. P. A. Abdulla, P. Bjesse, and N. Eén. Symbolic Reachability Analysis Based on SAT-Solvers. In TACAS, pages 411-425, March 2000.
2. J. A. Abraham, V. M. Vedula, and D. G. Saab. Verifying Properties Using Sequential ATPG. In Proc. of the International Test Conference (ITC02), October 2002.
3. V. D. Agrawal and S. T. Chakradhar. Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits. IEEE Trans. on CAD, 14(9):1155-1160, Sept. 1995.
4. A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu. Symbolic Model Checking without BDDs. In TACAS, pages 193-207, March 1999.
5. V. Boppana, S. P. Rajan, K. Takayama, and M. Fujita. Model Checking Based on Sequential ATPG. In Proc. of CAV, pages 418-430, July 1999.
6. th Design Automation Conference, pages 747-750, June 2002.
7. E. Goldberg and Y. Novikov. BerkMin: a Fast and Robust Sat-Solver. In Proc. of DATE, pages 142-149, March 2002.
8. R. Guo, S. M. Reddy, and I. Pomeranz. PROFTEST: A Property-Based Test Generator for Synchronous Sequential Circuits. IEEE Trans. on CAD, 22(8):1080-1091, August 2003.
9. P.-H. Ho, T. R. Shiple, K. Harer, J. H. Kukula, R. F. Damiano, V. Bertacco, J. Taylor, and J. Long. Smart Simulation Using Collaborative Formal and Simulation Engines. In Proc. of ICCAD, pages 120-126, Nov. 2000.
10. M. S. Hsiao, E. M. Rudnick, and J. H. Patel. Alternating strategies for sequential circuit ATPG. In Proc. of ED & TC, pages 368-374, March 1996.
11. M. S. Hsiao, E. M. Rudnick, and J. H. Patel. Sequential Circuit Test Generation Using Dynamic State Traversal. In Proc. of ED & TC, pages 22-28, March 1997.
12. th VTS, pages 263-269, April 2000.
13. th IEEE VLSI Test Symposium, pages 85-90, April 1993.
14. th Design Automation Conference, pages 263-268, June 1997.
15. T. Larrabee. Test Pattern Generation Using Boolean Satisfiability. IEEE Trans. on CAD, 11(1):4-15, Jan 1992.
16. X. Lin, I. Pomeranz, and S. M. Reddy. Techniques for Improving the Efficiency of Sequential Circuit Test Generation. In Proc. of ICCAD, pages 147-151, Nov. 1999.
17. F. Lu, L.-C. Wang, K.-T. Cheng, and R. C.-Y. Huang. A Circuit SAT Solver with Signal Correlation Guided Learning. In Proc. of the Design Automation & Test in Europe, March 2003.
18. J. P. Marques-Silva and K. A. Sakallah. GRASP: A Search Algorithm for Propositional Satisfiability. IEEE Trans. on Computers, 48(5):506-521, May 1999.
19. th DAC, pages 530-535, June 2001.
20. R. Mukherjee, J. Jain, K. Takayama, M. Fujita, J. Abraham, and D. Fussell. An Efficient Filter-based Approach for Combinational Verification. lEEE Trans. on CAD, 18:1542-1557, Nov. 1999.
21. T. Niermann and J. H. Patel. HITEC: A test generation package for sequential circuits. In Proc. of EDAC, pages 214-218, Feb. 1991.
22. th HLDVT, pages 177-182, November 2001.
23. M. R. Prasad, E. I. Goldberg, and R. K. Brayton. Using SAT for Combinational Equivalence Checking. In Proc. of DATE, pages 114-121, March 2001.
24. S. M. Reddy, I. Pomeranz, X. Lin, and N. Z. Basturkmen. New Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. In Proc. of VTS, April 1999.
25. nd DAC, pages 183-188, June 1995.
26. th International Conference on VLSI Design (VLSI'03), pages 243-248, January 2003.
27. M. Sheeran, S. Singh, and G. Stålmarck Checking safety properties using induction and a SAT-solver. In W. A. Hunt and S. D. Johnson, editors, Proc. of FMCAD, volume 1954, pages 108-125, Nov. 2000.
28. th DAC, pages 813-818, June 2002.
29. O. Shtrichman. Tuning SAT Checkers for Bounded Model Checking. In Proc. of CAV, pages 480-494, 2000.
30. O. Shtrichman. Pruning Techniques for the SAT-based Bounded Model Checking Problem. In Proc. of CHARME, Sept. 2001.
31. P. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. Combinational Test Generation Using Satisfiability. IEEE Trans. on CAD, 15(9):1167-1176, Sept. 1996.
32. C. Wang, S. M. Reddy, I. Pomeranz, X. Lin, and J. Rajski. Conflict Driven Techniques for Improving Deterministic Test Pattern Generation. In Proc. of ICCAD, pages 87-93, Nov. 2002.
33. H. Zhang. SATO: An Efficient Propositional Prover. In Proc. of CADE, pages 272-275, July 1997.