An efficient filter-based approach for combinational verification

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 11, 1999, Pages 1542-1557

  Mukherjee, Rajarshi ^a,b   Jain, Jawahar ^a,b   Takayama, Koichiro ^a,b   Fujita, Masahiro ^a,c   Abraham, Jacob A ^a,c   Fussell, Donald S ^a,c  

^a IEEE   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

Automatic test pattern generation (atpg); Binary decision diagrams (bdd's); Equivalence checking; Implications; Partitioning

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION (ATPG); BINARY DECISION DIAGRAMS (BDD); COMBINATIONAL VERIFICATION;

COMPUTATIONAL COMPLEXITY; DECISION THEORY; EQUIVALENCE CLASSES; HEURISTIC METHODS;

ELECTRIC NETWORK ANALYSIS;

EID: 0033345233     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.806801     Document Type: Article

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