Model checking based on sequential ATPG

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1633, Issue , 1999, Pages 418-430

  Boppana, Vamsi ^a   Rajan, Sreeranga P ^a   Takayama, Koichiro ^a   Fujita, Masahiro ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; COMPUTER AIDED ANALYSIS; COMPUTER CIRCUITS; TEMPORAL LOGIC;

CURRENT MODELING; EXPLORATION TECHNIQUES; HARDWARE DESIGN; INDUSTRIAL STRENGTH; SEQUENTIAL ATPG; STATE-SPACE EXPLOSION; SYNCHRONIZING SEQUENCE; TEMPORAL LOGIC PROPERTIES;

MODEL CHECKING;

EID: 84957068589     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48683-6_36     Document Type: Conference Paper

References (29)

1. [ABF90] M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital System Testing and Testable Design. New York, NY: Computer Science Press, 1990.
2. [AH96] R. Alur and T. A. Henzinger, editors. Computer-Aided Verification, CAV '96, volume 1102 of Lecture Notes in Computer Science, New Brunswick, NJ, July/August 1996. Springer-Verlag.
3. [Bop97] V. Boppana. State information-based solutions for sequential circuit diagnosis and testing. Technical Report CRHC-97-20, Ph.D. thesis, Center for Reliable and High-Performance Computing, University of Illinois at Urbana-Champaign, July 1997.
4. [Bry95] R.E. Bryant. Binary decision diagrams and beyond: Enabling technologies for formal verification. In Proceedings of the International Conference on Computer-Aided Design, pages 236-243, November 1995.
5. [CA89] K. T. Cheng and V. Agrawal. State Assignment for Initialilzable Synthesis. In Proc. Intl. Conf. Computer-Aided Design, pages 212-215, November 1989.
6. [CA93] K. T. Cheng and V. Agrawal. Initializability consideration in sequential machine synthesis. IEEE Trans. Computers, 41(3):374-379, March 1993.
7. [CGL94] E. Clarke, O. Grumberg, and D. Long. Verification tools for finite-state concurrent systems. In A Decade of concurrency-Reflections and Perspectives, volume 803 of Lecture Notes in Computer Science. Springer-Verlag, 1994.
8. [CM92] K. T. Cheng and H. K. T. Ma. On the over-specification problem in sequential ATPG algorithms. In Proc. Design Automation Conf., pages 16-21, June 1992.
9. [CM93] K. T. Cheng and H. K. T. Ma. On the over-specification problem in sequential ATPG algorithms. IEEETrans. Computer-Aided Design, 12(10):1599-1604, October 1993.
10. [FTMo83] M. Fujita, H. Tanaka, and T. Moto-oka. Verification with prolog and temporal logic. In Proc. of IFIP WG10.2 International Conference on Hardware Description Languages and their Applications, May 1983.
11. [FTMo85] M. Fujita, H. Tanaka, and T. Moto-oka. Logic design assistance with temporal logic. In Proc. of IFIP WG10.2 International Conference on Hardware Description Languages and their Applications, Aug. 1985.
12. [Goe90] P. Goel. An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEETrans. Computers, C-30(3):215-222, March 1990.
13. [Gro96] The VIS Group. VIS: A system for verification and synthesis. In Alur and Henzinger [AH96], pages 428-432.
14. [Hen68] F. C. Hennie. Finite-State Models for Logical Machines. New York, NY: John Wiley & Sons, Inc., 1968.
15. [HRP97] M. S. Hsiao, E. M. Rudnick, and J. H. Patel. Sequential circuit test generation using dynamic state traversal. In Proc. European Design and Test Conf., pages 22-28, March 1997.
16. [IN97] H. Iwashita and T. Nakata. Forward model checking techniques oriented to buggy designs. In Proc. Intl. Conf. Computer-Aided Design, pages 400-404, November 1997.
17. [INH96] H. Iwashita, T. Nakata, and F. Hirose. Ctl model checking based on forward state traversal. In Proc. Intl. Conf. Computer-Aided Design, pages 82-87, November 1996.
18. [Koh78] Z. Kohavi. Switching and Finite Automata Theory. New York, NY: McGraw-Hill, 1978.
19. [Kur94] R. P. Kurshan. Computer-Aided Verification of Coordinating Processes-The Automata-Theoretic Approach. Princeton University Press, Princeton, NJ, 1994.
20. [KV99] O. Kupferman and Moshe Y. Vardi. Model checking of safety properties. In CAV99, 1999.
21. [McM93] Kenneth L. McMillan. Symbolic Model Checking. Kluwer Academic Pub., Boston, MA, 1993.
22. [NFKT87] H. Nakamura, M. Fujita, S. Kono, and H. Tanaka. Temporal logic based fast verification systems using cover expressions. In Proc. of IFIP WG10.5 International Conference on VLSI, Aug. 1987.
23. [NP91] T. Niermann and J. H. Patel. HITEC: A test generation package for sequential circuits. In Proc. European Design Automation Conf., pages 214-218, February 1991.
24. [ORR+96] S. Owre, S. Rajan, J.M. Rushby, N. Shankar, and M.K. Srivas. PVS: Combining specification, proof checking, and model checking. In Alur and Henzinger [AH96], pages 411-414.
25. [Pel96] Doron Peled. Combining partial order reductions with on-the-fly model-checking. Formal Methods in System Design, 8(1):39-64, 1996.
26. [PR92] I. Pomeranz and S. M. Reddy. The multiple observation time test strategy. IEEE Trans. Computer-Aided Design, 40(5):627-637, May 1992.
27. [PR93] I. Pomeranz and S. M. Reddy. Classification of faults in synchronous sequential circuits. IEEETrans. Computers, 42(9):1066-1077, September 1993.
28. [TSNH98] K. Takayama, T. Satoh, T. Nakata, and F. Hirose. An approach to verify a large scale system-on-a-chip using symbolic model checking. In Proceedings of the International Conference on Computer Design, pages 308-313, October 1998.
29. [Wol82] P. Wolper. "synthesis of communicating processes from temporal logic specifications." Technical Report STAN-CS-82-925, Dept. of Computer Science, Stanford University, 1982.