An analysis of ATPG and SAT algorithms for formal verification

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2001-January, Issue , 2001, Pages 177-182

  Parthasarathy, G ^a   Huang, Chung Yang ^b   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Verplex Systems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FORMAL VERIFICATION; RECONFIGURABLE HARDWARE;

BREADTH-FIRST; DEPTH FIRST; HARDWARE VERIFICATION; INDUSTRIAL CIRCUITS; REAL CIRCUITS; SATISFIABILITY; TWO-STATE;

AUTOMATIC TEST PATTERN GENERATION;

EID: 0346868422     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2001.972826     Document Type: Conference Paper

References (16)

1. A. Biere, A. Cimatti, E.M. Clarke, M. Fujita, and Y.Zhu. Symbolic Model Checking using Sat Procedures instead of BDDs. In 36th ACM/IEEE Design Automation Conference (DAC), pages 317-320, June 1999.
2. C.-Y. Huang and K.-T. Cheng. Assertion Checking by Combined Word-level ATPG and Modular Arithmetic Constraint-Solving Techniques. In 37th ACM/IEEE Design Automation Conference (DAC), June 2000.
3. C.-Y. Huang and K.-T. Cheng. Using Word-Level atpg and Modular Arithmetic Constraint-Solving for Assertion Property Checking. IEEE Trans. on CAD of Integrated Circuits and Systems, 20(3):381-391, June 2001.
4. E. Gizdarski and H. Fujiwara. SPIRIT: A Highly Robust Combinational Test Generation Algorithm. In Proc. IEEE VLSI Test Symposium (VTS), pages 346-351, Los Angeles, USA, Apr. 2001.
5. E.I. Goldberg, M.R. Prasad, and R.K. Brayton. Using sat for combinational equivalence checking. In Proc. Design, Automation and Test in Europe (DATE' 01), March 2001.
6. I. Hamzaoglu and J. Patel. New Techniques for Deterministic Test Pattern Generation. In Proc. IEEE VLSI Test Symposium (VTS), pages 446-452. IEEE Computer Society Press, April 1998.
7. J.P Marques-Silva and K.A. Sakallah. Grasp - A Search Algorithm for Propositional Satisfiability. IEEE Trans. on Computers, 48(5):506-521, May 1999.
8. J.Th. van der Linden, M.H. Konijnenburg, and A.J. van de Goor. Test Generation and Three-state Elements, Busses, and Bidirectionals. In Proc. IEEE VLSI Test Symposium (VTS), pages 114-121, Cherry Hill, NJ, USA, May 1994. IEEE Computer Society Press.
9. K.-T. Cheng and A. Krstic. Current Directions in Automatic Test-Pattern Generation. IEEE Computer, 32(11):58-64, 1999.
10. M. Moskiewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Engineering an Efficient SAT Solver. In 38th ACM/IEEE Design Automation Conference (DAC), 2001.
11. M.N. Velev and R.E. Bryant. Effective use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Processors. In 38th Design Automation Conference (DAC), pages 226-231, June 2001.
12. P. Tafertshofer, A. Ganz, and K. Antreich. Igraine - An Implication-Graph based Engine for Fast Implication, Justification and Propagation. IEEE Trans. on Computer-Aided Design, 19(8):907-927, August 2000.
13. P. Tafertshofer, A. Ganz, and M. Hentfling. A SAT-Based Implication Engine for Efficient ATPG, Equivalence Checking, Optimization of Netlists. In Proc. Int. Conference on Computer-Aided Design (ICCAD), pages 648-655, Nov. 1997.
14. R.E. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Trans. on Computers, C-35(8):677-691, August 1986.
15. S.-Y. Huang, K.-T. Cheng, K.-C. Chen, C.-Y. Huang, and F. Brewer. AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. on Computers, 49(5):443-464, 2000.
16. H. Zhang. SATO: an Efficient Propositional Prover. In Proc. of the 17th Int. Conference of Automated Deduction, pages 272-275. Springer-Verlag, 1997.