Formal verification using bounded model checking: SAT versus sequential ATPG engines

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 243-248

  Saab, D G ^a   Abraham, J A ^b   Vedula, V M ^b  

^a Case Western Reserve University   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

Automatic test pattern generation; Boolean functions; Computer bugs; Data structures; Design engineering; Engines; Formal verification; Jacobian matrices; Logic design; Testing

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; BOOLEAN FUNCTIONS; DATA STRUCTURES; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ENGINES; JACOBIAN MATRICES; LOGIC DESIGN; MODEL CHECKING; SYSTEMS ANALYSIS; TESTING;

BOUNDED MODEL CHECKING; COMPUTER BUGS; DESIGN ENGINEERING; DIGITAL DESIGNS; PROPERTY VERIFICATION; SATISFIABILITY SOLVERS; SEQUENTIAL ATPG; VERIFICATION TECHNIQUES;

FORMAL VERIFICATION;

EID: 2342610523     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183144     Document Type: Conference Paper

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