Testing, verification, and diagnosis in the presence of unknowns

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 263-269

  Jain, A ^a   Boppana, V ^a   Mukherjee, R ^a   Jain, J ^a   Fujita, M ^a   Hsiao, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; CONSTRAINT THEORY; ELECTRONICS INDUSTRY; ERROR ANALYSIS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; PROBLEM SOLVING;

AUTOMATIC TEST PATTERN GENERATION; BOOLEAN SATISFIABILITY; EQUIVALENCE CHECKING; ERROR DIAGNOSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0033741773     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (12)